Texas Instruments ADC3683EVM

Overview

ADC3683EVM from Texas Instruments is an evaluation module designed to characterize the ADC3683 18-bit, 65 MSPS high-speed SAR analog-to-digital converter. It supports external or onboard CDCE6214 clocking, transformer-coupled (ADT1-6T+) or FDA-driven (THS4541) analog inputs, and outputs serialized LVDS data at up to 1 Gbps via FMC connector for capture on TSW1400EVM.

For engineers reviewing the ADC3683EVM datasheet, ADC3683EVM pinout, ADC3683EVM application, or ADC3683EVM equivalent, this page provides verified hardware configuration details, real/complex decimation mode setup, power monitoring capability via INA226, FDA input modification guidance, and LVDS interposer interface requirements for FPGA-based data capture.

Technical Context

The ADC3683EVM implements a dual-channel, 18-bit, 65 MSPS SAR ADC evaluation platform with serial LVDS output compliant with SLVDS standards. It integrates a CDCE6214 programmable clock generator for onboard sampling clock (65 MHz) and DCLKIN (292.5 MHz) generation, and supports three digital interface modes: 1-Wire, 2-Wire, and 1/2-Wire serialization.

Hardware flexibility includes jumper-configurable power sourcing (USB or external +5 V), SPI-controlled ADC register access via FTDI FT4234H, and selectable analog input paths - balun-coupled (3.2 Vpp full-scale, -1 dBFS nominal) or FDA-driven (THS4541, gain = 2.5, 20 MHz LPF). Power consumption is monitored per rail (+1.8 V AVDD/IOVDD) using INA226 current shunt monitors.

Key Specifications

Availability

ADC3683EVM is available at Aetrix Electronics and suitable for high-speed data acquisition, RF receiver prototyping, and precision test equipment development requiring stable component supply and validated reference design integration.

Supply support for ADC3683EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data converter technologies, with decades of leadership in precision ADC architecture and evaluation system design.

The ADC368xEVM product line is part of TI's High-Speed Data Converter Evaluation Platform family, engineered to accelerate validation of SAR ADCs in demanding applications including communications infrastructure, medical imaging, and automated test equipment.

FAQ

What is the primary function of the ADC3683EVM?

The ADC3683EVM is a dedicated evaluation module for the ADC3683 18-bit, 65 MSPS SAR analog-to-digital converter. Its purpose is to enable engineers to validate dynamic performance (SNR, SFDR), configure decimation modes (bypass, real, complex), evaluate analog input options (balun vs. FDA), and interface the ADC's serial LVDS output with FPGA-based capture systems like the TSW1400EVM. The ADC3683EVM itself contains no ADC die - it hosts and exercises the ADC3683 device.

Does the ADC3683EVM include the ADC3683 IC, or is it sold separately?

Yes, the ADC3683EVM includes the ADC3683 IC mounted on the board as the core device under test. The EVM is a complete, assembled evaluation platform - not just a carrier board. The ADC3683 is soldered onto the PCB and fully integrated with supporting circuitry including clock conditioning, analog front-end options, power regulation (TPS62231), and LVDS signal routing to the FMC connector.

What clock frequencies are required for basic operation of the ADC3683EVM in bypass mode?

For default bypass (non-decimating) operation, the ADC3683EVM requires a 65 MHz sample clock applied to SMA connector J4 and a 292.5 MHz DCLKIN applied to SMA connector J7. These frequencies correspond to the ADC3683's 65 MSPS sampling rate in 2-Wire interface mode with 4.5× DCLKIN multiplier. Both clocks must be frequency-locked to prevent data scrambling during capture.

Can the ADC3683EVM operate without external signal generators?

Yes - the ADC3683EVM supports onboard clocking using its integrated CDCE6214 clock generator. With hardware modifications (e.g., installing R41/R51 and R60/R62, removing R46/R47/R35/R36), the CDCE6214 can synthesize both the 65 MHz sample clock and 292.5 MHz DCLKIN from a single reference. This eliminates the need for two external signal generators and simplifies initial functional verification, though external clocks are recommended for full AC performance evaluation.

How is analog input configured on the ADC3683EVM, and what are the key differences between options?

The ADC3683EVM offers two analog input configurations: transformer-coupled (default, using ADT1-6T+ baluns) and FDA-driven (using THS4541 fully differential amplifier). Balun input delivers superior SNR but lower SFDR; FDA input improves SFDR by ~5–8 dBFS at the cost of ~2–3 dBFS SNR degradation. Selection requires physical component changes (e.g., installing R1/R2/R14 and removing C3/C6/R7/R8 for FDA path), and both support 3.2 Vpp full-scale with –1 dBFS operating point.