Texas Instruments ADC3910D125IRSMR
- Part No.:
- ADC3910D125IRSMR
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
ADC3910D125IRSMR.pdf
- Description:
- 10-BIT, TWO-CHANNEL, 125-MSPS AD
- Quantity:
- Payment:

- Shipping:

Inventory:1,627
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Product details
Overview
ADC3910D125IRSMR from Texas Instruments is a dual-channel, 10-bit, 125MSPS analog-to-digital converter with 1-clock-cycle latency, 92mW power consumption at full speed, buffered differential inputs (150MHz bandwidth), and single 1.8V supply with optional 3.3V IO support. It targets low-latency control loops and LiDAR receiver front-ends requiring deterministic timing and compact integration.
For engineers reviewing the ADC3910D125IRSMR datasheet, ADC3910D125IRSMR pinout, ADC3910D125IRSMR application, or ADC3910D125IRSMR equivalent, key selection criteria include guaranteed 1-cycle latency, dual-channel crosstalk <90dBFS at 20MHz, SNR of 60.6dBFS at 125MSPS/5MHz input, DDR/SDR/serial CMOS interface flexibility, and industrial temperature operation from –40°C to +105°C.
Technical Context
The ADC3910D125IRSMR implements a pipelined architecture optimized for ultra-low latency: conversion completes in one clock cycle, with no pipeline registers added beyond the sampling stage. Its on-chip digital comparators provide per-channel event-triggered interrupts with programmable thresholds and hysteresis-enabling real-time anomaly detection without host CPU intervention.
It supports multiple output interfaces-including DDR and SDR parallel CMOS (12-bit bus), 2-/4-lane serial CMOS, and configurable DCLK/FCLK modes-with timing parameters explicitly specified for 125MSPS operation. The integrated input buffer accepts differential or single-ended signals up to 1.9Vpp full-scale, and the device operates with either internal 1.2V reference or external reference with 12kΩ input impedance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Sampling Rate | 125 MSPS - enables digitization of IF signals up to 62.5 MHz (Nyquist) in direct-sampling receivers. |
| Latency | 1 clock cycle - guarantees deterministic signal-to-data delay for closed-loop control systems with sub-8 ns response time at 125 MHz. |
| Power Consumption | 92 mW at 125 MSPS - allows dual-channel high-speed acquisition in thermally constrained embedded modules without active cooling. |
| SNR / SFDR | 60.6 dBFS / 64 dBc at 125 MSPS, fIN = 5 MHz - sufficient for 9.8 ENOB in precision time-of-flight measurement applications. |
| Analog Input Bandwidth | 150 MHz (–3 dB) - supports wideband RF/IF sampling with minimal amplitude roll-off up to L-band frequencies. |
| Supply Voltage | 1.8 V AVDD, 1.8–3.3 V IOVDD - enables interoperability with both low-voltage FPGAs and legacy 3.3 V logic without level shifters. |
| Operating Temperature | –40°C to +105°C - qualified for under-hood automotive sensing, industrial LiDAR, and outdoor test equipment deployments. |
Pinout & Package
VQFN-32 (RSM) package, 4mm × 4mm body with exposed thermal pad; RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INAP / INAM | Differential analog input, Channel A | Accepts buffered 1.9 Vpp differential signal; common-mode voltage set by internal VCM (1.25 V) or external bias. |
| INBP / INBM | Differential analog input, Channel B | Active only in dual-channel mode (ADC3910Dx); NC on single-channel variants. |
| CLK | Sampling clock input | Accepts 5–125 MHz LVCMOS clock; aperture jitter ≤500 fs enables high-SFDR performance. |
| D0–D11 | Parallel digital output data lanes | 12-bit CMOS outputs supporting DDR (default) or SDR; each lane rated for 250 MHz toggle rate. |
| DCLK / DCLK/FCLK | Data clock or frame clock output | Programmable via SPI: default inverse DCLK for DDR timing alignment; selectable frame clock for synchronization. |
| OEN/PD | Output enable / power-down control | Active-low pin; asserts global power-down mode (4 mW) or disables digital outputs while ADC remains active. |
| ALERT | Digital comparator status output | Open-drain interrupt flag indicating threshold violation per channel; supports hysteresis and event counting. |
| SEN / SCLK / SDIO | 3-wire SPI configuration interface | 20 MHz max clock; used for register programming, decimation ratio selection, and comparator threshold setup. |
Key Features
| Feature | Design Value |
|---|---|
| 1-cycle latency mode | Enables real-time feedback in servo control and adaptive optics where loop closure must occur within one sample period. |
| Dual independent digital comparators | Per-channel high/low threshold + hysteresis eliminates false triggers from noise; event counter logs occurrences without CPU polling. |
| On-chip decimation filter | Configurable decimation ratios (2/4/8/16) reduce output data rate and bus bandwidth while preserving signal integrity for baseband processing. |
| Flexible digital interface | Hardware-selectable DDR/SDR/serial CMOS modes allow optimization for FPGA pin count, timing margin, or PCB routing density. |
| Buffered analog inputs | Eliminates need for external op-amp drivers; supports 150 MHz bandwidth with 7 pF input capacitance and 1.25 V common-mode output. |
Applications
| LiDAR Time-of-Flight Receiver | Laser Scanner Signal Acquisition |
|---|---|
|
Use Scenario: Digitizing fast-rising return pulses from pulsed laser diodes in short-range 3D mapping systems. IC Role / Device Role / Timing Role: Dual-channel ADC capturing synchronized echo and reference waveforms with sub-8 ns timing resolution. Use Value: 1-cycle latency ensures precise pulse edge alignment; 150 MHz input bandwidth preserves pulse fidelity for <10 cm distance resolution. |
Use Scenario: Sampling position-encoded analog signals from galvanometer mirror feedback sensors in high-speed laser marking systems. IC Role / Device Role / Timing Role: Low-power dual ADC acquiring mirror angle and velocity data at 125 MSPS for closed-loop motion correction. Use Value: 92 mW total power enables integration into compact scanner heads; industrial temp range supports factory-floor reliability. |
| Radio Receiver Baseband Digitization | Source Measure Unit (SMU) Feedback Loop |
|
Use Scenario: Direct sampling of IF signals in SDR transceivers operating below 62.5 MHz, avoiding image-reject mixers. IC Role / Device Role / Timing Role: Dual ADC providing I/Q digitization with <90 dBFS inter-channel isolation at 20 MHz. Use Value: 60.6 dBFS SNR at 125 MSPS/5 MHz meets LTE/WiFi dynamic range requirements; DDR interface reduces FPGA pin count. |
Use Scenario: Real-time current/voltage monitoring in semiconductor parametric testers during device characterization sweeps. IC Role / Device Role / Timing Role: High-accuracy ADC feeding feedback path in SMU's nested control loop for sub-microsecond settling. Use Value: ±1 LSB INL and no missing codes ensure traceable metrology-grade measurements; 1-cycle latency tightens loop bandwidth. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, low-latency ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS52J90IRGCT | 10-bit, 8-channel, 100 MSPS; higher channel count but 3-cycle latency and 225 mW power at full rate. | Better suited for multi-sensor data acquisition; less optimal for latency-critical control loops. | Select when system requires >2 channels and can tolerate higher latency and power. |
| AD9234BCPZ-125 | 12-bit, dual-channel, 125 MSPS; 1.25 V supply only, no 3.3 V IO option, and 2-cycle latency. | Higher resolution for precision instrumentation; lacks digital comparators and decimation filtering. | Select when ENOB >10 bits is mandatory and on-chip event detection is unnecessary. |
Compared with ADS52J90IRGCT and AD9234BCPZ-125, the ADC3910D125IRSMR uniquely balances ultra-low latency (1 cycle), dual-channel integration, built-in digital monitoring, and flexible IO voltage-making it optimal for space-constrained, real-time embedded systems where deterministic timing and autonomous event response are critical.
Availability
ADC3910D125IRSMR is available at Aetrix Electronics and suitable for LiDAR receiver modules, laser scanner control units, and radio baseband digitization systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ADC3910D125IRSMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance data converters and signal chain solutions.
The ADC3910 family was designed specifically for ultra-low-latency, low-power, dual-channel digitization in space- and power-constrained real-time systems-including industrial sensing, optical time-of-flight, and adaptive control applications.
FAQ
What is the minimum latency achievable with the ADC3910D125IRSMR?
The ADC3910D125IRSMR achieves a fixed latency of exactly 1 clock cycle in low-latency mode-verified across the full –40°C to +105°C temperature range and at all supported sampling rates up to 125 MSPS. This latency is hardware-defined and does not vary with interface configuration, decimation settings, or input signal conditions. The ADC3910D125IRSMR delivers deterministic timing critical for closed-loop control systems where jitter or variable delay would degrade stability.
Does the ADC3910D125IRSMR support external voltage reference operation?
Yes, the ADC3910D125IRSMR supports both internal 1.2 V reference and external reference via the VREF pin. When using external reference, the device accepts a 1.2 V ±1% source with 12 kΩ input impedance and recommends 10 μF + 0.1 μF bypass capacitors placed adjacent to the VREF pin. External reference reduces gain drift to –35 ppm/°C versus –102 ppm/°C with internal reference, improving accuracy over temperature in precision measurement applications using the ADC3910D125IRSMR.
How does the dual digital comparator function in the ADC3910D125IRSMR?
The ADC3910D125IRSMR integrates two independent digital comparators-one per analog channel-that monitor converted data against user-programmed high/low thresholds and hysteresis values. Each comparator generates an ALERT output pulse and increments an internal event counter upon threshold crossing. This enables autonomous anomaly detection (e.g., overvoltage, signal loss) without host processor involvement, reducing system-level latency and CPU load in safety-critical or real-time monitoring applications using the ADC3910D125IRSMR.
What digital interface modes does the ADC3910D125IRSMR support?
The ADC3910D125IRSMR supports DDR CMOS (default for dual-channel), SDR CMOS, and 2-/4-lane serial CMOS output interfaces-all configurable via SPI. DDR mode uses DCLK and D0–D11 for 12-bit parallel data at double data rate; SDR uses same pins at single rate; serial CMOS reduces pin count by multiplexing data across fewer lanes with programmable frame clock. All modes maintain 1-cycle latency in low-latency mode, and IOVDD supports 1.8 V or 3.3 V logic levels-ensuring compatibility with diverse FPGA and ASIC receivers interfacing with the ADC3910D125IRSMR.
Is the ADC3910D125IRSMR pin-compatible with other members of the ADC3910 family?
Yes, the ADC3910D125IRSMR is pin-compatible with all ADC3910Dx (dual-channel) and ADC3910Sx (single-channel) variants in the same VQFN-32 (RSM) package, including ADC3910D025IRSMR and ADC3910D065IRSMR. Pin functions, power domains, and interface signaling are identical across speed grades and channel counts. This allows design reuse and sampling-rate scalability without PCB redesign-enabling rapid prototyping and production variant management using the ADC3910D125IRSMR alongside lower-speed family members.
ADC3910D125IRSMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 10
- Sampling Rate (Per Second):
- 125M
- Number of Inputs:
- 2, 4
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel, Serial
- Configuration:
- ADC
- Ratio - S/H:ADC:
- 0:2
- Number of A/D Converters:
- 2
- Architecture:
- -
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V, 3.2V ~ 3.4V
- Features:
- -
- Operating Temperature:
- -40°C ~ 105°C
- Supplier Device Package:
- 32-VQFN (4x4)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADC3910D125IRSMR FAQ
1.How can I place an order for ADC3910D125IRSMR through Aetrix?
Please submit a Request for Quotation (RFQ) for ADC3910D125IRSMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADC3910D125IRSMR reliable?
The price and inventory of ADC3910D125IRSMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC3910D125IRSMR is usually 5 days.
3.What payment methods are accepted for ADC3910D125IRSMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADC3910D125IRSMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADC3910D125IRSMR?
ADC3910D125IRSMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADC3910D125IRSMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADC3910D125IRSMR?
For technical support, including ADC3910D125IRSMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC3910D125IRSMR requirements.
6.How does Aetrix verify that ADC3910D125IRSMR is sourced from the original manufacturer or authorized distributors?
All ADC3910D125IRSMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC3910D125IRSMR meets industry standards.
7.What is the process for return or replacement of ADC3910D125IRSMR?
All ADC3910D125IRSMR units undergo pre-shipment inspection (PSI). If there is an issue with ADC3910D125IRSMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADC3910D125IRSMR part is unused and in its original packaging.
Return procedure for ADC3910D125IRSMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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