Texas Instruments ADC3910D125IRSMT

Overview

ADC3910D125IRSMT from Texas Instruments is a dual-channel, 10-bit, 125MSPS analog-to-digital converter with 1-clock-cycle latency, 150MHz input bandwidth, and buffered differential inputs. It operates from a single 1.8V analog supply (with optional 3.3V IO), delivers 60.6dBFS SNR at 5MHz input, and targets low-latency control loops and LiDAR signal acquisition.

For engineers reviewing the ADC3910D125IRSMT datasheet, ADC3910D125IRSMT pinout, ADC3910D125IRSMT application, or ADC3910D125IRSMT equivalent, key selection criteria include guaranteed 1-cycle latency, dual-channel 125MSPS operation with no missing codes, industrial temperature support (–40°C to +105°C), and flexible DDR/SDR/serial CMOS output interface compatibility.

Technical Context

The ADC3910D125IRSMT implements a pipelined ADC architecture optimized for deterministic timing: aperture jitter is 500fs, conversion time is fixed at 5.5ns across all sampling rates, and wake-up from power-down takes ≤30µs with internal reference. Its on-chip digital comparators provide per-channel event-triggered interrupts with programmable thresholds and hysteresis.

It supports both internal (1.2V) and external reference configurations, features an integrated VCM buffer (1.25V output), and enables real-time decimation (×2/4/8/16) via on-chip digital filtering - configurable independently per channel without altering latency path in low-latency mode.

Key Specifications

Pinout & Package

VQFN-32 (4mm × 4mm) package with exposed thermal pad; RoHS-compliant, moisture-sensitive level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed, low-latency ADC applications.

Compared with ADC3910D065IRSMT and ADC3910S125IRSMT, the ADC3910D125IRSMT uniquely delivers dual-channel 125MSPS operation with guaranteed 1-cycle latency - making it the only option among the three for time-coherent I/Q sampling at full speed without sacrificing determinism.

Availability

ADC3910D125IRSMT is available at Aetrix Electronics and suitable for LiDAR signal acquisition, low-latency motion control, GPS/GNSS front-end digitization, and source measure unit instrumentation requiring stable component supply and industrial temperature qualification.

Supply support for ADC3910D125IRSMT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADC3910 family was designed specifically for ultra-low-latency, low-power, high-speed digitization in space-constrained industrial and sensing systems - emphasizing deterministic timing, flexible interface options, and robust operation across extended temperature ranges.

FAQ

What is the minimum and maximum sampling clock frequency supported by the ADC3910D125IRSMT?

The ADC3910D125IRSMT supports a sampling clock frequency range of 5MHz to 125MHz, as specified in the Absolute Maximum Ratings and Recommended Operating Conditions sections of the datasheet. Operation below 5MHz is not characterized or guaranteed, and exceeding 125MHz violates absolute maximum limits and may cause functional failure. The device achieves its rated 125MSPS performance only within this defined window.

Does the ADC3910D125IRSMT require an external reference, or can it operate with an internal reference?

The ADC3910D125IRSMT supports both internal and external reference configurations. It includes a factory-trimmed 1.2V internal reference (±0.8% gain error) that requires no external components. Alternatively, a precision 1.2V external reference can be applied to the VREF pin for improved accuracy (±0.2% gain error). The reference source is selected via SPI register configuration - no hardware change is needed.

How does the 1-clock-cycle latency mode function in the ADC3910D125IRSMT, and what interface modes support it?

The 1-clock-cycle latency mode in the ADC3910D125IRSMT routes sampled data directly through a minimal pipeline with no added registers. It is enabled by default in DDR mode for dual-channel devices and SDR mode for single-channel variants. Enabling serial CMOS or decimation adds latency (5–270 cycles depending on configuration), so true 1-cycle operation requires using parallel DDR or SDR output with low-latency mode activated via register bit.

What is the purpose of the ALERT pin on the ADC3910D125IRSMT, and how is it configured?

The ALERT pin on the ADC3910D125IRSMT is an open-drain digital output that asserts when either channel's analog input exceeds programmable high/low thresholds. It is configured via SPI-accessible comparator registers, supporting hysteresis, event counting, and channel masking. No host CPU polling is required - the pin provides hardware-level interrupt signaling for over-range or window violation events.

Can the ADC3910D125IRSMT interface directly with a 3.3V FPGA I/O bank, and what supply voltage is required for that operation?

Yes, the ADC3910D125IRSMT can interface directly with a 3.3V FPGA I/O bank using its IOVDD supply. When IOVDD is set to 3.3V (within 3.2–3.4V recommended range), all digital outputs (D0–D11, DCLK, ALERT) swing rail-to-rail between 0V and 3.3V, meeting LVCMOS33 input thresholds. AVDD remains at 1.8V; no level-shifting circuitry is required.