Texas Instruments ADC78H89CIMT/NOPB
- Part No.:
- ADC78H89CIMT/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ADC78H89CIMT/NOPB.pdf
- Description:
- IC ADC 12BIT SAR 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADC78H89CIMT/NOPB from Texas Instruments is a 12-bit, 7-channel, 500 KSPS successive-approximation ADC with independent analog (AVDD: 2.7–5.25 V) and digital (DVDD: 2.7 V to AVDD) supplies, SPI/QSPI/MICROWIRE-compatible serial interface, and TSSOP-16 packaging. It serves as a low-power data acquisition front-end in portable instrumentation and automotive sensor systems.
For engineers reviewing the ADC78H89CIMT/NOPB datasheet, ADC78H89CIMT/NOPB pinout, ADC78H89CIMT/NOPB application, or ADC78H89CIMT/NOPB equivalent, key selection criteria include its 7 analog input channels, ±1 LSB INL/DNL, 1.5 mW typical power at 3 V, industrial temperature range (−40°C to +85°C), and track-and-hold architecture enabling single-cycle full-resolution acquisition after power-up.
Technical Context
The ADC78H89CIMT/NOPB implements a charge-redistribution SAR architecture with internal track-and-hold, requiring exactly 16 SCLK cycles per conversion (13 for conversion + 3 for acquisition). Its control register is loaded on the first 8 rising SCLK edges of each frame, enabling channel selection (AIN1–AIN7 or GND) via ADD2–ADD0 bits before sampling.
Digital I/O operates referenced to DVDD but voltage-limited by AVDD; analog inputs accept 0 V to AVDD with 3 pF hold-mode capacitance and 33 pF track-mode capacitance. Power-down is asserted by pulling CS high, reducing supply current to 0.1 µA and power consumption to 0.3 µW at 3 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - guarantees monotonicity and full-scale code coverage across operating range. |
| Sample Rate | 500 KSPS minimum - supports real-time monitoring of fast-changing sensor signals in embedded control loops. |
| INL / DNL | ±1 LSB maximum - ensures accurate multi-channel calibration without software correction in precision measurement systems. |
| Power (3 V) | 1.5 mW typical in active mode - enables battery-powered operation for >1 year in low-duty-cycle data loggers. |
| Supply Range | AVDD: 2.7–5.25 V; DVDD: 2.7 V to AVDD - allows flexible dual-supply partitioning to isolate analog noise from digital switching. |
| Interface | SPI/QSPI/MICROWIRE/DSP-compatible serial - interoperates directly with TI C2000, ARM Cortex-M, and FPGA soft peripherals without level-shifting. |
| Temperature Range | −40°C to +85°C - qualified for under-hood automotive navigation and industrial field transmitters. |
Pinout & Package
ADC78H89CIMT/NOPB is housed in a 16-lead Thin Shrink Small Outline Package (TSSOP), with exposed pad omitted and JEDEC MO-153 compliant footprint. Pin 1 is CS (chip select); pins 4 and 12 are GND (internally tied); AVDD (pin 3) and DVDD (pin 13) require separate 0.1 µF ceramic + 1 µF tantalum bypassing within 1 cm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS (Pin 1) | Chip Select | Falling edge initiates conversion and loads Control Register; high state forces full shutdown (0.1 µA). |
| AIN1–AIN7 (Pins 5–11) | Analog Inputs | Seven single-ended channels accepting 0 V to AVDD; selected via ADD2–ADD0 bits in Control Register. |
| AVDD (Pin 3) | Analog Supply | Primary reference and analog rail (2.7–5.25 V); must be quieter than DVDD to maintain 72.8 dB SNR. |
| DVDD (Pin 13) | Digital Supply | Digital core rail (2.7 V to AVDD); must not exceed AVDD by >300 mV to prevent ESD diode conduction. |
| SCLK (Pin 16) | Serial Clock | 50 kHz–8 MHz clock; falling edges drive conversion timing and data output; rising edges load Control Register. |
| DOUT (Pin 15) | Data Output | MSB-first straight binary; outputs four leading zeros followed by 12 data bits over 16 SCLK cycles. |
| DIN (Pin 14) | Data Input | Loads Control Register bits (ADD2–ADD0, DONTC) on first 8 rising SCLK edges of each frame. |
| GND (Pins 4, 12) | Ground Return | Single internal node; analog and digital grounds must be connected externally at one point to avoid ground bounce. |
Key Features
| Feature | Design Value |
|---|---|
| Independent AVDD/DVDD supplies | Enables split-plane PCB layout with dedicated analog ground pour and ferrite-bead isolation for DVDD. |
| Variable power management | CS-controlled shutdown reduces current to 0.1 µA-no external enable logic required for ultra-low-power sleep modes. |
| Single-cycle full-resolution acquisition | No power-up delay or dummy conversions needed; first sample after reset is valid at full 12-bit accuracy. |
| 7-channel multiplexed input | Reduces BOM count vs. discrete ADCs; eliminates need for external analog mux in multi-sensor nodes (e.g., engine coolant, oil pressure, intake temp). |
| Straight binary output coding | Eliminates two's-complement sign extension overhead in firmware; simplifies DSP FFT and filtering pipelines. |
Applications
| Automotive Navigation Sensors | Portable Medical Monitoring |
|---|---|
Use Scenario: Simultaneous sampling of vehicle yaw rate, lateral acceleration, and wheel speed signals in inertial measurement units (IMUs) for dead-reckoning navigation. IC Role / Device Role / Timing Role: 7-channel SAR ADC digitizing analog sensor outputs at 500 KSPS with synchronized channel sequencing via Control Register. Use Value: Enables sub-degree heading accuracy using correlated multi-axis data without external sample-and-hold or timing controller. | Use Scenario: Battery-powered ECG/SpO₂ monitor acquiring lead-I, lead-II, respiration, and pulse oximetry analog waveforms. IC Role / Device Role / Timing Role: Low-power 12-bit ADC providing simultaneous 7-channel acquisition with <1.5 mW active power at 3 V. Use Value: Extends clinical-grade device runtime beyond 72 hours on a single CR2032 coin cell while maintaining ±1 LSB linearity. |
| Industrial Process Transmitters | Mobile Communication Baseband |
Use Scenario: 4–20 mA loop-powered field transmitter measuring temperature, pressure, and valve position in hazardous environments. IC Role / Device Role / Timing Role: Precision ADC interfacing isolated sensor bridges and RTDs, operating across −40°C to +85°C with AVDD as reference. Use Value: Delivers 11.8 ENOB and 88 dB SFDR to resolve microvolt-level bridge imbalances without external amplification. | Use Scenario: RF front-end calibration in LTE/Wi-Fi access points requiring real-time IQ imbalance correction via baseband ADC feedback. IC Role / Device Role / Timing Role: High-fidelity ADC capturing DC-coupled baseband I/Q paths with 72.8 dB SNR and −90 dB IMD3. Use Value: Supports closed-loop digital predistortion (DPD) with <0.01% gain/phase error across 40 kHz bandwidth. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 12-bit SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS7822U | 8-bit resolution, 200 KSPS, single-channel, MSOP-8 package | Lacks multiplexing and resolution for multi-sensor systems; suitable only for cost-sensitive single-input designs | Select only when 8-bit accuracy and lower throughput suffice and board space is constrained. |
| ADS8320EB | 16-bit resolution, 100 KSPS, single-channel, SOIC-8; no internal track-and-hold | Higher resolution but slower speed and no on-chip multiplexer-requires external analog switching and driver amplifiers | Choose when absolute precision outweighs channel count and power efficiency in lab-grade instruments. |
Compared with ADS7822U and ADS8320EB, ADC78H89CIMT/NOPB uniquely balances 7-channel integration, 500 KSPS throughput, and 12-bit linearity in a single TSSOP-16 package-making it optimal for compact, multi-signal embedded data loggers where power, size, and channel density are co-constrained.
Availability
ADC78H89CIMT/NOPB is available at Aetrix Electronics and suitable for automotive navigation sensors, portable medical monitoring devices, and industrial process transmitters requiring stable component supply across extended product lifecycles.
Supply support for ADC78H89CIMT/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 90 years of innovation in precision signal chain solutions.
The ADC78H89CIMT/NOPB belongs to TI's precision data acquisition portfolio, designed specifically for low-power, multi-channel sensor interfacing in harsh industrial and mobile environments where reliability and supply-chain resilience are critical.
FAQ
What is the maximum clock frequency supported by ADC78H89CIMT/NOPB?
The ADC78H89CIMT/NOPB supports a maximum SCLK frequency of 8 MHz, with guaranteed performance at that rate. Minimum clock frequency is 50 kHz. At 8 MHz, the device achieves its rated 500 KSPS throughput, completing each 12-bit conversion in exactly 16 SCLK cycles (13 for conversion + 3 for acquisition). Operating below 50 kHz violates timing specifications and may cause data corruption.
Does ADC78H89CIMT/NOPB require an external reference voltage?
No, ADC78H89CIMT/NOPB uses AVDD as its internal reference voltage-no external reference is needed. The LSB size equals AVDD / 4096, so full-scale range is 0 V to AVDD. This simplifies design and reduces BOM count, but requires AVDD to be low-noise and stable; TI recommends bypassing AVDD with 0.1 µF ceramic + 1 µF tantalum capacitors placed within 1 cm of the pin.
How does ADC78H89CIMT/NOPB handle power supply sequencing?
ADC78H89CIMT/NOPB requires AVDD to be applied before or concurrently with DVDD; DVDD must not exceed AVDD by more than 300 mV to prevent ESD diode conduction at the analog inputs. Incorrect sequencing risks latch-up or erratic conversion behavior. The device draws no current from DVDD until AVDD is present above 2.7 V, enforcing safe startup in systems with independent regulators.
Can ADC78H89CIMT/NOPB perform continuous conversions without gaps?
Yes-ADC78H89CIMT/NOPB supports gapless continuous conversion when CS is held low. Each conversion takes 16 SCLK cycles, and the next begins immediately after the previous completes. Throughput remains fixed at 500 KSPS when SCLK = 8 MHz. If CS is pulsed, a 1-sample delay occurs between Control Register update and corresponding output due to pipelined architecture.
What is the input impedance and drive requirement for ADC78H89CIMT/NOPB analog channels?
ADC78H89CIMT/NOPB presents 33 pF input capacitance in track mode and 3 pF in hold mode, with multiplexer on-resistance ~500 Ω. To avoid settling errors and distortion, it must be driven by a source impedance ≤1 kΩ. For AC-critical applications (e.g., audio, RF calibration), TI recommends buffering with a low-output-impedance op amp such as OPA350 to fully charge the 30 pF sampling capacitor within the 3-SCLK acquisition window.
ADC78H89CIMT/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 500k
- Number of Inputs:
- 7
- Input Type:
- Single Ended
- Data Interface:
- SPI, DSP
- Configuration:
- MUX-S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- Supply
- Voltage - Supply, Analog:
- 2.7V ~ 5.25V
- Voltage - Supply, Digital:
- 2.7V ~ 5.25V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 16-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADC78H89CIMT/NOPB FAQ
1.How can I place an order for ADC78H89CIMT/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for ADC78H89CIMT/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADC78H89CIMT/NOPB reliable?
The price and inventory of ADC78H89CIMT/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADC78H89CIMT/NOPB is usually 5 days.
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ADC78H89CIMT/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADC78H89CIMT/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADC78H89CIMT/NOPB?
For technical support, including ADC78H89CIMT/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADC78H89CIMT/NOPB requirements.
6.How does Aetrix verify that ADC78H89CIMT/NOPB is sourced from the original manufacturer or authorized distributors?
All ADC78H89CIMT/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADC78H89CIMT/NOPB meets industry standards.
7.What is the process for return or replacement of ADC78H89CIMT/NOPB?
All ADC78H89CIMT/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with ADC78H89CIMT/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADC78H89CIMT/NOPB part is unused and in its original packaging.
Return procedure for ADC78H89CIMT/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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