Analog Devices Inc. ADCMP561BRQ

Overview

ADCMP561BRQ from Analog Devices is a dual high-speed PECL comparator in 16-lead QSOP package, delivering 700 ps propagation delay, 75 ps overdrive dispersion, and −2.0 V to +3.0 V input common-mode range. It features differential latch control, internal pull-up resistors on latch inputs, and robust input protection - deployed in automatic test equipment front ends and high-speed line receivers.

For engineers reviewing the ADCMP561BRQ datasheet, ADCMP561BRQ pinout, ADCMP561BRQ application, or ADCMP561BRQ equivalent, key selection criteria include propagation delay stability across overdrive, PECL-compatible differential outputs with 500 ps rise/fall times, latch timing parameters (tS = 250 ps, tH = 250 ps), programmable hysteresis capability (via external resistor on ADCMP562 only), and industrial temperature range support (−40°C to +85°C).

Technical Context

The ADCMP561BRQ uses Analog Devices' proprietary XFCB process to achieve sub-nanosecond timing precision. Its differential input stage maintains consistent propagation delay across a wide −2.0 V to +3.0 V common-mode range, while complementary PECL outputs drive 50 Ω loads terminated to VDD − 2 V without external level-shifting.

Latch enable inputs (LEA/LEB) operate in active-low mode with internal pull-ups, enabling track-and-hold or sample-and-hold operation. The device supports three independent supply rails: VCC = +5.0 V, VEE = −5.2 V, and VDD = +3.3 V, with PSRR > 85 dB on all supplies and ESD protection exceeding 4 kV HBM.

Key Specifications

Pinout & Package

ADCMP561BRQ is housed in a 16-lead QSOP package (JEDEC MO-137-AB compliant) with 0.635 mm lead pitch and 5.0 mm × 4.0 mm body size. Thermal resistance θ_JA = 104°C/W in still air.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed comparator applications.

Compared with ADCMP562BRQ, ADCMP561BRQ offers identical speed and noise performance in a smaller 16-pin package but lacks hysteresis control. Against MAX9601ASA+, ADCMP561BRQ delivers superior channel matching and wider input range at the cost of more complex supply sequencing and larger board area.

Availability

ADCMP561BRQ is available at Aetrix Electronics and suitable for automatic test equipment, high-speed instrumentation, and oscilloscope front-end designs requiring stable component supply across extended production lifecycles.

Supply support for ADCMP561BRQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADCMP561BRQ belongs to Analog Devices' high-speed comparator product line, engineered specifically for sub-nanosecond timing accuracy in test, measurement, and communications infrastructure.

FAQ

What is the maximum operating frequency supported by the ADCMP561BRQ?

The ADCMP561BRQ supports a maximum toggle rate exceeding 800 MHz under conditions of >50% output swing. This is enabled by its 550 ps rise time and 470 ps fall time, combined with 1.5 GHz equivalent input rise time bandwidth. For reliable operation at full speed, proper PECL termination (50 Ω to VDD − 2 V) and controlled-impedance PCB routing are required. The ADCMP561BRQ achieves this performance across the full −40°C to +85°C industrial temperature range.

Does the ADCMP561BRQ support single-supply operation?

No, the ADCMP561BRQ requires three separate supply rails: VCC = +4.75 V to +5.25 V, VEE = −4.96 V to −5.45 V, and VDD = +2.5 V to +5.0 V. This triple-supply architecture enables its −2.0 V to +3.0 V input common-mode range and PECL-compatible output swing. Attempting single-supply operation violates absolute maximum ratings and will damage the device or cause functional failure. The ADCMP561BRQ datasheet specifies no single-supply configuration.

How does the latch function work on the ADCMP561BRQ?

The ADCMP561BRQ provides independent latch enable inputs (LEA/LEA for Channel A, LEB/LEB for Channel B) that operate in active-low mode. When the latch enable pair is held high, the comparator operates in tracking mode; when pulled low, it captures and holds the input state at the moment of transition. Internal pull-up resistors set the default to tracking mode if latch inputs are left unconnected. Latch timing parameters - including 250 ps setup/hold time and 600 ps latch-to-output delay - are specified in the ADCMP561BRQ datasheet under Table 1.

Can unused comparator channels on the ADCMP561BRQ be left floating?

No, unused comparator channels on the ADCMP561BRQ must not be left floating. Due to the device's high internal gain, floating inputs may cause oscillation that affects both channels. To disable Channel B, for example, tie +INB and −INB to fixed voltages at least one diode drop apart (e.g., +INB = 0 V, −INB = −0.7 V), and connect LEB/LEB to appropriate logic levels (e.g., LEB = VDD, LEB = VDD − 2 V) to force tracking mode. These requirements are explicitly documented in the ADCMP561BRQ Applications Information section.

What is the purpose of the VDD − 2 V termination requirement for ADCMP561BRQ outputs?

The ADCMP561BRQ PECL outputs are open-emitter and require termination to VDD − 2 V through 50 Ω resistors to establish correct logic high/low voltage levels (VOH ≈ VDD − 0.81 V, VOL ≈ VDD − 1.54 V). This matches standard PECL-10K/10KH logic families and ensures signal integrity, impedance matching, and minimal reflections. Using 50 Ω to ground or other terminations violates the ADCMP561BRQ's output stage design and results in incorrect logic levels or excessive current draw.