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Home > Products > Integrated Circuits (ICs) > Linear > Comparators

Analog Devices Inc. ADCMP562BRQZ

Name: ADCMP562BRQZ
Brand: Analog Devices Inc.
SKU: ADCMP562BRQZ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADCMP562BRQZ

Manufacturer:: Analog Devices Inc.

Category:: Comparators

Package:: 20-SSOP (0.154", 3.90mm Width)

Datasheet:: ADCMP562BRQZ.pdf

Description:: IC COMPARATOR 2 W/LATCH 20QSOP

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Product details

Overview

ADCMP562BRQZ from Analog Devices is a dual high-speed PECL comparator with programmable hysteresis, designed for precision timing-critical signal conditioning in ATE and instrumentation front ends. It delivers 700 ps propagation delay, 75 ps overdrive dispersion, 1.5 GHz equivalent input rise time bandwidth, and operates across −40°C to +85°C with −2.0 V to +3.0 V input common-mode range.

For engineers reviewing the ADCMP562BRQZ datasheet, ADCMP562BRQZ pinout, ADCMP562BRQZ application, or ADCMP562BRQZ equivalent, key selection considerations include latch-enable timing (250 ps setup/hold), PECL-compatible differential outputs (500 ps rise/fall), programmable hysteresis via HYSA/HYSB pins, and dual-supply operation (VCC = +5 V, VEE = −5.2 V, VDD = +3.3 V).

Technical Context

The ADCMP562BRQZ integrates two independent high-speed comparators on Analog Devices' XFCB process, each featuring a differential input stage with robust input protection and internal latch pull-up resistors. Its propagation delay dispersion of ≤75 ps across 20 mV–1.5 V overdrive ensures consistent timing in jitter-sensitive applications like clock recovery and high-speed triggers.

Unlike the ADCMP561, the ADCMP562BRQZ includes dedicated HYSA and HYSB pins enabling independent, resistor-programmable hysteresis per channel (20 mV at RHYS = 19.5 kΩ; 70 mV at RHYS = 8.0 kΩ), decoupled from output swing and symmetric about the trip point - critical for noise-immune threshold detection in disk drive read channels and patient diagnostics.

Key Specifications

Parameter	Value and Actual Design Meaning
Propagation Delay	700 ps at 1 V overdrive - enables sub-nanosecond timing alignment in high-speed sampling circuits.
Overdrive Dispersion	75 ps (20 mV–1.5 V) - minimizes timing uncertainty when input slew varies, essential for ATE pattern generators.
Input Common-Mode Range	−2.0 V to +3.0 V - supports direct interfacing with bipolar, ECL, and LVDS sources without level-shifting.
Output Rise/Fall Time	550 ps / 470 ps (10%–90%) - drives 50 Ω PECL loads terminated to VDD − 2.0 V with minimal ringing.
Hysteresis Programmability	Per-channel via HYSA/HYSB pins - allows independent noise margin tuning (20–70 mV) for asymmetric signal paths.
Supply Voltages	VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V - triple-rail operation supports legacy PECL logic compatibility and low-noise analog sensing.
Operating Temperature	−40°C to +85°C - qualified for industrial and medical embedded systems including hand-held test instruments.

Pinout & Package

ADCMP562BRQZ is housed in a 20-lead QSOP package (JEDEC MO-137-AB compliant), with 0.65 mm lead pitch and exposed pad not electrically connected. Thermal resistance θ_JA = 80°C/W in still air.

Pin/Terminal	Circuit Role	Design Meaning
1, 4, 20	VDD	Logic supply terminal (+2.5 V to +5.0 V); powers PECL output stage and latch circuitry.
2, 3	QA, QA	Differential PECL outputs for Channel A - drive 50 Ω loads to VDD − 2.0 V with complementary logic states.
5, 6	LEA, LEA	Complementary latch enable inputs for Channel A - active-low latching; internal pull-ups default to tracking mode if open.
7	VEE	Negative analog supply (−4.96 V to −5.45 V); sets input stage bias and common-mode operating point.
8	−INA	Inverting analog input for Channel A - must be paired with +INA; accepts −2.0 V to +3.0 V common-mode signals.
9	+INA	Noninverting analog input for Channel A - differential pair with −INA; defines comparison threshold.
10	HYSA	Programmable hysteresis current input for Channel A - connects to GND via resistor (8–19.5 kΩ) to set 20–70 mV hysteresis.
11	HYSB	Programmable hysteresis current input for Channel B - independent of HYSA; enables asymmetric noise immunity per channel.
12, 13	+INB, −INB	Noninverting/inverting inputs for Channel B - identical electrical specs to Channel A; fully independent operation.
14	VCC	Positive analog supply (+4.75 V to +5.25 V); powers input differential pair and internal bias networks.
15, 16	LEB, LEB	Complementary latch enable inputs for Channel B - functionally identical to LEA/LEA but isolated for dual-channel control.
17	GND	Analog ground reference - requires low-inductance connection to minimize ground bounce in high-speed layouts.
18, 19	QB, QB	Differential PECL outputs for Channel B - fully matched to QA/QA in delay, skew, and drive strength.

Key Features

Feature	Design Value
Dual independent comparators	Enables simultaneous window detection or redundant timing paths without inter-channel crosstalk or skew.
Programmable hysteresis per channel	Eliminates need for external feedback networks; supports channel-specific noise margins in mixed-signal front ends.
75 ps overdrive dispersion	Reduces timing jitter in automatic test equipment where input amplitude varies across test vectors.
Internal latch pull-up resistors	Allows latch-enable pins to float for default tracking mode - simplifies PCB layout and reduces component count.
PECL-compatible differential outputs	Directly drives 50 Ω transmission lines terminated to VDD − 2.0 V, avoiding level translators in high-speed digital interfaces.

Applications

High-Speed Window Comparator	Logic Analyzer Front End
Use Scenario: Detecting whether an analog signal lies between two precise voltage thresholds in real time, such as in disk drive read channel signal integrity monitoring. IC Role / Device Role / Timing Role: Dual-channel comparator implementing upper/lower bound detection with independent hysteresis (HYSA/HYSB) to reject noise near trip points. Use Value: 700 ps propagation delay and 75 ps dispersion ensure tight timing correlation between window edges, minimizing false trigger events during rapid signal transitions.	Use Scenario: Converting high-frequency analog waveforms from DUTs into clean digital logic levels for capture and analysis in benchtop logic analyzers. IC Role / Device Role / Timing Role: High-bandwidth signal restoration stage - transforms degraded, low-swing waveforms into full-swing PECL-compatible outputs synchronized to system clock. Use Value: 1.5 GHz equivalent input rise time bandwidth and 500 ps output transitions preserve edge fidelity up to 800 MHz toggle rate, enabling accurate timing measurement.
Peak Detection Trigger	Zero-Crossing Detector
Use Scenario: Generating precise strobe pulses at local maxima of periodic waveforms in patient diagnostic equipment (e.g., ECG waveform analysis). IC Role / Device Role / Timing Role: Comparator configured with fast latch enable to sample and hold peak amplitude; HYSA sets hysteresis to suppress noise-induced false peaks. Use Value: 250 ps latch setup/hold times and 600 ps latch-to-output delay allow sub-nanosecond triggering accuracy relative to analog envelope peaks.	Use Scenario: Detecting polarity reversals in AC-coupled sensor signals (e.g., vibration transducers, audio preamps) with minimal phase error. IC Role / Device Role / Timing Role: Precision zero-reference comparator using internal offset voltage matching (±2.0 mV channel-to-channel) and wide common-mode range (−2.0 V to +3.0 V). Use Value: Input offset tempco of 2.0 µV/°C and CMRR ≥80 dB maintain <10 mV trip-point drift over industrial temperature range, ensuring stable crossing detection.

High-Speed Window Comparator

Logic Analyzer Front End

Use Scenario: Detecting whether an analog signal lies between two precise voltage thresholds in real time, such as in disk drive read channel signal integrity monitoring.

IC Role / Device Role / Timing Role: Dual-channel comparator implementing upper/lower bound detection with independent hysteresis (HYSA/HYSB) to reject noise near trip points.

Use Value: 700 ps propagation delay and 75 ps dispersion ensure tight timing correlation between window edges, minimizing false trigger events during rapid signal transitions.

Use Scenario: Converting high-frequency analog waveforms from DUTs into clean digital logic levels for capture and analysis in benchtop logic analyzers.

IC Role / Device Role / Timing Role: High-bandwidth signal restoration stage - transforms degraded, low-swing waveforms into full-swing PECL-compatible outputs synchronized to system clock.

Use Value: 1.5 GHz equivalent input rise time bandwidth and 500 ps output transitions preserve edge fidelity up to 800 MHz toggle rate, enabling accurate timing measurement.

Peak Detection Trigger

Zero-Crossing Detector

Use Scenario: Generating precise strobe pulses at local maxima of periodic waveforms in patient diagnostic equipment (e.g., ECG waveform analysis).

IC Role / Device Role / Timing Role: Comparator configured with fast latch enable to sample and hold peak amplitude; HYSA sets hysteresis to suppress noise-induced false peaks.

Use Value: 250 ps latch setup/hold times and 600 ps latch-to-output delay allow sub-nanosecond triggering accuracy relative to analog envelope peaks.

Use Scenario: Detecting polarity reversals in AC-coupled sensor signals (e.g., vibration transducers, audio preamps) with minimal phase error.

IC Role / Device Role / Timing Role: Precision zero-reference comparator using internal offset voltage matching (±2.0 mV channel-to-channel) and wide common-mode range (−2.0 V to +3.0 V).

Use Value: Input offset tempco of 2.0 µV/°C and CMRR ≥80 dB maintain <10 mV trip-point drift over industrial temperature range, ensuring stable crossing detection.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed comparator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADCMP561BRQZ	No hysteresis pins; single VDD pin; 16-lead QSOP; identical speed and dispersion specs.	Lacks per-channel hysteresis programming - unsuitable where asymmetric noise immunity is required.	Select ADCMP561BRQZ only when hysteresis is implemented externally or unnecessary.
MAX999ESA+	Single-channel, 4.5 ns propagation delay, CMOS/TTL outputs, no latch, 8-lead SOIC.	Lower speed and no latch/hysteresis features - limited to non-critical, cost-sensitive digital interfacing.	Choose MAX999ESA+ only for general-purpose, non-timing-critical threshold detection with single-ended outputs.

Compared with ADCMP562BRQZ, ADCMP561BRQZ offers identical speed and dual-channel architecture but omits programmable hysteresis - making it a functional subset for simpler designs. MAX999ESA+ trades speed and feature depth for cost and package simplicity, serving entry-level applications where nanosecond timing and latch control are unnecessary.

Availability

ADCMP562BRQZ is available at Aetrix Electronics and suitable for automatic test equipment, high-speed instrumentation, and medical diagnostics requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADCMP562BRQZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADCMP562BRQZ belongs to Analog Devices' high-speed comparator product line, engineered specifically for sub-nanosecond timing accuracy, low-jitter signal restoration, and robust operation in ATE, oscilloscopes, and medical instrumentation front ends.

FAQ

What is the maximum toggle rate supported by the ADCMP562BRQZ?

The ADCMP562BRQZ supports a maximum toggle rate of 800 MHz under conditions of >50% output swing. This capability stems from its 700 ps propagation delay, 500 ps output rise/fall times, and 1.5 GHz equivalent input rise time bandwidth - all verified across the industrial temperature range (−40°C to +85°C). The ADCMP562BRQZ maintains this performance with proper PECL termination (50 Ω to VDD − 2.0 V) and low-inductance layout practices.

How does the hysteresis function differ between ADCMP562BRQZ and ADCMP561BRQZ?

The ADCMP562BRQZ includes dedicated HYSA and HYSB pins enabling independent, resistor-programmable hysteresis per channel (20–70 mV), while the ADCMP561BRQZ lacks hysteresis pins entirely. In ADCMP562BRQZ, hysteresis is generated by a current source referenced to GND, making it symmetrical and output-swing-independent - a key advantage over external positive-feedback methods. This distinction makes ADCMP562BRQZ suitable for noise-prone applications like patient diagnostics where channel-specific noise margins are required.

What are the recommended power supply sequencing requirements for ADCMP562BRQZ?

Analog Devices specifies no strict power supply sequencing for ADCMP562BRQZ, but recommends powering VEE (−5.2 V) first, followed by VCC (+5.0 V), then VDD (+3.3 V) to ensure stable biasing of the differential input stage before enabling outputs. This sequence minimizes transient stress during startup and avoids undefined output states. All supplies must remain within absolute maximum ratings: VCC (−0.5 V to +6.0 V), VEE (−6.0 V to +0.5 V), and VDD (−0.5 V to +6.0 V) relative to GND.

Can ADCMP562BRQZ operate with a single 5 V supply?

No, ADCMP562BRQZ requires three distinct supply rails: VCC = +5.0 V (positive analog), VEE = −5.2 V (negative analog), and VDD = +3.3 V (logic/PECL output). Its input stage is designed for wide common-mode operation (−2.0 V to +3.0 V), which necessitates dual-polarity analog supplies. Attempting single-supply operation violates absolute maximum ratings and will result in non-functional or damaged devices. The ADCMP562BRQZ is incompatible with single-rail architectures unless external level-shifting and biasing networks are added - negating its high-speed advantages.

What is the purpose of the complementary latch enable pins (e.g., LEA and LEA) on ADCMP562BRQZ?

The complementary latch enable pins (LEA/LEA and LEB/LEB) on ADCMP562BRQZ implement differential latch control to reject common-mode noise on control lines and ensure robust sampling in noisy environments. When driven differentially, they eliminate ambiguity in latch state definition; if left unconnected, internal pull-ups force LEA/LEB high and LEA/LEB low - defaulting both channels to tracking mode. This architecture enables precise track-and-hold or sample-and-hold operation with 250 ps setup/hold times and 600 ps latch-to-output delay, critical for high-speed data acquisition systems using ADCMP562BRQZ.

ADCMP562BRQZ Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Package/Case:: 20-SSOP (0.154", 3.90mm Width)

Series:: -

Packaging:: Tube

Product Status:: Active

Type:: with Latch

Number of Elements:: 2

Output Type:: Complementary, Differential, Open-Emitter, PECL

Voltage - Supply, Single/Dual (±):: ±4.75V ~ 5.25V

:: 2mV @ -5.2V,5V

Voltage - Input Offset (Max):: 3µA @ -5.2V,5V

Current - Input Bias (Max):: 30mA

Current - Output (Typ):: 5mA, 28mA, 13mA

Current - Quiescent (Max):: 80dB CMRR, 85dB PSRR

CMRR, PSRR (Typ):: 0.83ns

Propagation Delay (Max):: ±1mV

Hysteresis:: -40°C ~ 85°C

Operating Temperature:: -

Grade:: -

Qualification:: Surface Mount

:: 20-QSOP

ADCMP562BRQZ FAQ

1.How can I place an order for ADCMP562BRQZ through Aetrix?

Please submit a Request for Quotation (RFQ) for ADCMP562BRQZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADCMP562BRQZ reliable?

The price and inventory of ADCMP562BRQZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADCMP562BRQZ is usually 5 days.

3.What payment methods are accepted for ADCMP562BRQZ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADCMP562BRQZ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADCMP562BRQZ?

ADCMP562BRQZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADCMP562BRQZ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADCMP562BRQZ?

For technical support, including ADCMP562BRQZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADCMP562BRQZ requirements.

6.How does Aetrix verify that ADCMP562BRQZ is sourced from the original manufacturer or authorized distributors?

All ADCMP562BRQZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADCMP562BRQZ meets industry standards.

7.What is the process for return or replacement of ADCMP562BRQZ?

All ADCMP562BRQZ units undergo pre-shipment inspection (PSI). If there is an issue with ADCMP562BRQZ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADCMP562BRQZ part is unused and in its original packaging.

Return procedure for ADCMP562BRQZ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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