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Analog Devices Inc. ADCMP564BRQ
- Part No.:
- ADCMP564BRQ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Comparators
- Package:
- 20-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
ADCMP564BRQ.pdf
- Description:
- IC COMPARATOR 2 W/LATCH 20QSOP
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
ADCMP564BRQ from Analog Devices is a dual, high-speed ECL comparator IC designed for precision timing-critical signal conditioning in test and measurement systems. It delivers 700 ps propagation delay, 75 ps overdrive dispersion, ±2.0 V to +3.0 V input common-mode range, and programmable hysteresis via dedicated HYS pins - enabling robust threshold detection in automatic test equipment front ends.
For engineers reviewing the ADCMP564BRQ datasheet, ADCMP564BRQ pinout, ADCMP564BRQ application, or ADCMP564BRQ equivalent, key selection considerations include latch-enable timing (200 ps setup/hold), ECL-compatible differential outputs (−1.95 V to −0.81 V), channel-to-channel skew (≤50 ps), and hysteresis programmability (20 mV to 70 mV with external resistors).
Technical Context
The ADCMP564BRQ integrates two independent high-speed comparators on Analog Devices' XFCB process, each featuring a differential ECL-input stage with 750 kΩ differential and 1.8 MΩ common-mode input resistance. Its latch enable architecture supports tracking, track-and-hold, and sample-and-hold modes via complementary LEA/LEB inputs with internal pull-ups.
Unlike the ADCMP563, the ADCMP564BRQ includes two dedicated hysteresis control pins (HYSA, HYSB) that accept external resistors to set symmetrical, output-swing-independent hysteresis (20–70 mV). Its propagation delay remains stable across −40°C to +85°C (0.25 ps/°C tempco) and over 1 V to 20 mV overdrive (700–830 ps).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Propagation Delay | 700 ps at 1 V overdrive - enables sub-nanosecond timing alignment in ATE trigger paths. |
| Overdrive Dispersion | 75 ps (20 mV–1.5 V) - ensures consistent timing across varying input amplitudes in noisy signal environments. |
| Input Common-Mode Range | −2.0 V to +3.0 V - supports direct interfacing with wide-swing analog sources without level-shifting. |
| Hysteresis Programmability | 20 mV (RHYS = 23.5 kΩ) or 70 mV (RHYS = 9.0 kΩ) - allows noise-immune threshold setting without feedback parasitics. |
| Output Drive | ECL-compatible differential outputs driving 50 Ω to −2.0 V - eliminates need for external line drivers in high-speed interconnects. |
| Supply Rejection | >85 dB PSRR on both VCC and VEE - maintains timing accuracy under noisy power rail conditions. |
| Operating Temperature | −40°C to +85°C industrial range - validated for embedded instrumentation and bench equipment deployment. |
Pinout & Package
ADCMP564BRQ is packaged in a 20-lead QSOP (Quad Small Outline Package) with exposed pad. Pin 1 is −INA; pins 11 and 12 are HYSA and HYSB respectively; complementary latch enables (LEA/LEA, LEB/LEB) and outputs (QA/QA, QB/QB) are arranged for matched trace routing. GND pins (4, 7, 17, 20) support low-inductance grounding.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | −INA | Inverting input for Channel A - must be driven differentially with +INA (Pin 9) to maintain common-mode stability. |
| 2, 3 | QA, QA | Complementary ECL outputs for Channel A - directly drive 50 Ω terminated lines to −2.0 V without buffering. |
| 4, 7, 17, 20 | GND | Analog ground connections - multiple pins reduce ground loop inductance for high-frequency signal integrity. |
| 5, 6 | LEA, LEA | Complementary latch enable for Channel A - active-low latching; open-circuit defaults to tracking mode via internal pull-up. |
| 8 | VEE | Negative supply (−5.2 V typical) - powers internal ECL circuitry and sets output logic low level. |
| 9 | +INA | Noninverting input for Channel A - paired with −INA (Pin 1); differential input voltage range: −5 V to +5 V. |
| 10 | HYSA | Hysteresis control for Channel A - sinking current sets symmetrical hysteresis; RHYS to GND defines magnitude. |
| 11 | −INB | Inverting input for Channel B - electrically identical to −INA but isolated for independent dual-channel operation. |
| 12 | HYSB | Hysteresis control for Channel B - independent of HYSA; enables asymmetric hysteresis per channel if needed. |
| 13, 14 | QB, QB | Complementary ECL outputs for Channel B - matched rise/fall times (450–530 ps) ensure deterministic dual-channel timing. |
| 15 | VCC | Positive supply (+5.0 V typical) - powers output stage; PSRR >85 dB minimizes supply-induced jitter. |
| 16, 18, 19 | LEB, LEB, +INB | Complementary latch enable and noninverting input for Channel B - identical timing specs to Channel A counterparts. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent latch-enable channels | Enables synchronized track-and-hold across two signal paths with 200 ps setup/hold and 500 ps latch-to-output delay. |
| Programmable hysteresis per channel | Eliminates external feedback networks; 20–70 mV hysteresis set by single resistor per HYSA/HYSB pin. |
| 75 ps overdrive dispersion | Reduces timing uncertainty in variable-amplitude signals - critical for window comparators and peak detectors. |
| 1.5 GHz equivalent input bandwidth | Supports clean edge detection on fast-rising signals (e.g., 133 MHz clock edges with 2.6 ns rise time). |
| ECL-compatible differential outputs | Drives 50 Ω transmission lines directly to −2.0 V, avoiding level translators and preserving signal fidelity up to 800 MHz toggle rate. |
| Robust input protection | Withstands −3.0 V to +4.0 V common-mode and −7.0 V to +7.0 V differential input transients per Absolute Maximum Ratings. |
Applications
| Automatic Test Equipment (ATE) Triggering | High-Speed Oscilloscope Front End |
|---|---|
|
Use Scenario: Detecting precise edge crossings of stimulus signals to initiate digitizer sampling in modular ATE systems. IC Role / Device Role / Timing Role: Dual-channel comparator providing sub-nanosecond trigger latency with matched propagation between channels for multi-channel synchronization. Use Value: 700 ps propagation delay and ≤50 ps channel-to-channel skew enable deterministic timing capture across 16+ DUT channels. |
Use Scenario: Converting analog waveform inputs into clean digital logic levels for timebase and trigger generation in real-time oscilloscopes. IC Role / Device Role / Timing Role: High-bandwidth signal restoration stage before FPGA-based time interpolation and display processing. Use Value: 1.5 GHz equivalent input bandwidth and 500 ps output rise/fall preserve fast transient fidelity for >1 GHz analog bandwidth scopes. |
| Window Comparator for Peak Detection | High-Speed Line Receiver with Hysteresis |
|
Use Scenario: Monitoring pulse amplitude envelopes in medical diagnostics equipment to flag out-of-range cardiac signal peaks. IC Role / Device Role / Timing Role: Dual comparator configured as upper/lower threshold detector with independent hysteresis on each channel (HYSA/HYSB). Use Value: Programmable 20–70 mV hysteresis per channel suppresses false triggers from ECG baseline noise without degrading response speed. |
Use Scenario: Recovering degraded high-speed serial data from long PCB traces or cables in logic analyzers and protocol testers. IC Role / Device Role / Timing Role: Signal restoration comparator with latch enable used to capture and hold valid data windows during clock recovery. Use Value: 75 ps overdrive dispersion and 200 ps latch setup time ensure accurate data sampling even with amplitude-varying eye diagrams. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed comparator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADCMP563BRQ | Same 16-lead QSOP package, identical speed (700 ps delay), no hysteresis pins - lacks HYSA/HYSB functionality. | Not suitable where noise immunity requires per-channel hysteresis; requires external hysteresis network if needed. | Select ADCMP563BRQ only when dual-channel comparison without programmable hysteresis suffices and board space is constrained. |
| MAX999ESA+ | Single-channel, 4.5 ns propagation delay, CMOS/TTL outputs, 3.3 V supply - slower, lower voltage, no ECL compatibility. | Applicable only in non-ECL, lower-speed (<100 MHz) digital threshold detection with relaxed timing budgets. | Choose MAX999ESA+ only for cost-sensitive, low-power, single-ended applications where ECL performance is unnecessary. |
Compared with ADCMP564BRQ, ADCMP563BRQ omits hysteresis control but shares pinout compatibility for Channel A/B I/O; MAX999ESA+ trades speed and ECL drive for simplicity and single-supply operation - neither offers drop-in replacement capability due to functional and interface differences.
Availability
ADCMP564BRQ is available at Aetrix Electronics and suitable for automatic test equipment, high-speed oscilloscope front ends, and medical diagnostic instrumentation requiring stable component supply across extended production lifecycles.
Supply support for ADCMP564BRQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The ADCMP564BRQ belongs to Analog Devices' high-speed comparator product line, engineered specifically for sub-nanosecond timing accuracy in test, measurement, and instrumentation systems operating under demanding signal integrity requirements.
FAQ
What is the function of the HYSA and HYSB pins on the ADCMP564BRQ?
The HYSA and HYSB pins on the ADCMP564BRQ provide independent, resistor-programmable hysteresis for Channels A and B respectively. Each pin sinks current proportional to an external resistor tied to GND, generating symmetrical hysteresis (20 mV or 70 mV) centered on the trip point - eliminating output-swing dependency and parasitic feedback issues found in traditional positive-feedback hysteresis schemes. This design is exclusive to the ADCMP564BRQ and not present in the ADCMP563BRQ.
Does the ADCMP564BRQ support true ECL-level signaling?
Yes, the ADCMP564BRQ provides fully ECL-compatible differential outputs (QA/QA, QB/QB) specified for 50 Ω termination to −2.0 V, delivering VOH = −0.81 V and VOL = −1.95 V under load. Its output stage drives transmission lines directly without level shifters, and its input common-mode range (−2.0 V to +3.0 V) accepts standard ECL logic swings. The device meets ECL 10K/10KH family interface requirements per its datasheet specifications.
How does the latch enable functionality work on the ADCMP564BRQ?
The ADCMP564BRQ features complementary latch enable inputs (LEA/LEA for Channel A, LEB/LEB for Channel B) that operate in active-low mode. When the latch enable signal transitions low, the comparator captures and holds the input state at that instant; when high, it operates in transparent tracking mode. Internal pull-up resistors default unconnected inputs to tracking mode. Setup and hold times are both 200 ps, and latch-to-output delay is 500 ps - enabling precise sample-and-hold control in high-speed data acquisition systems using the ADCMP564BRQ.
Can the ADCMP564BRQ operate from a single supply?
No, the ADCMP564BRQ requires dual supplies: VCC = +4.75 V to +5.25 V and VEE = −4.96 V to −5.45 V. Its internal ECL circuitry and output stage depend on this negative rail to establish proper logic thresholds and drive capability. Attempting single-supply operation violates Absolute Maximum Ratings and will result in nonfunctional or damaged units. The datasheet specifies no single-supply configuration, and all timing, DC, and AC performance data assume dual-rail operation.
What is the maximum toggle rate supported by the ADCMP564BRQ?
The ADCMP564BRQ supports a maximum toggle rate of 800 MHz under conditions of >50% output swing and 50% duty cycle, as specified in the Rev. D datasheet. This rating reflects its ability to sustain full logic transitions at high frequency without degradation in propagation delay or jitter. Real-world performance depends on proper layout, termination (50 Ω to −2.0 V), and bypassing (1 µF + 10 nF per supply pin), as outlined in the "Optimizing High Speed Performance" section of the ADCMP564BRQ datasheet.
ADCMP564BRQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Package/Case:
- 20-SSOP (0.154", 3.90mm Width)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- with Latch
- Number of Elements:
- 2
- Output Type:
- Complementary, Differential, ECL, Open-Emitter
- Voltage - Supply, Single/Dual (±):
- ±4.75V ~ 5.25V
- :
- 2mV @ -5.2V,5V
- Voltage - Input Offset (Max):
- 3µA @ -5.2V,5V
- Current - Input Bias (Max):
- 30mA
- Current - Output (Typ):
- 5mA, 25mA
- Current - Quiescent (Max):
- 80dB CMRR, 85dB PSRR
- CMRR, PSRR (Typ):
- 0.83ns
- Propagation Delay (Max):
- ±1mV
- Hysteresis:
- -40°C ~ 85°C
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- Surface Mount
- :
- 20-QSOP
ADCMP564BRQ FAQ
1.How can I place an order for ADCMP564BRQ through Aetrix?
Please submit a Request for Quotation (RFQ) for ADCMP564BRQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADCMP564BRQ reliable?
The price and inventory of ADCMP564BRQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADCMP564BRQ is usually 5 days.
3.What payment methods are accepted for ADCMP564BRQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADCMP564BRQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADCMP564BRQ?
ADCMP564BRQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADCMP564BRQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADCMP564BRQ?
For technical support, including ADCMP564BRQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADCMP564BRQ requirements.
6.How does Aetrix verify that ADCMP564BRQ is sourced from the original manufacturer or authorized distributors?
All ADCMP564BRQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADCMP564BRQ meets industry standards.
7.What is the process for return or replacement of ADCMP564BRQ?
All ADCMP564BRQ units undergo pre-shipment inspection (PSI). If there is an issue with ADCMP564BRQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADCMP564BRQ part is unused and in its original packaging.
Return procedure for ADCMP564BRQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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