Analog Devices Inc. ADCMP606BKSZ-R2
- Part No.:
- ADCMP606BKSZ-R2
- Manufacturer:
- Analog Devices Inc.
- Category:
- Comparators
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
ADCMP606BKSZ-R2.pdf
- Description:
- IC COMPARATOR 1 GEN PUR SC70-6
- Quantity:
- Payment:

- Shipping:

Inventory:4,986
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADCMP606BKSZ-R2 from Analog Devices is a rail-to-rail, single-supply CML comparator optimized for high-speed signal conditioning in timing-critical systems. It delivers 1.25 ns propagation delay, 2.5 ps RMS random jitter, and operates from 2.5 V to 5.5 V supply with input common-mode range from −0.2 V to VCCI + 0.2 V. Used in clock/data restoration and high-speed line receivers where sub-nanosecond timing fidelity is required.
For engineers reviewing the ADCMP606BKSZ-R2 datasheet, ADCMP606BKSZ-R2 pinout, ADCMP606BKSZ-R2 application, or ADCMP606BKSZ-R2 equivalent, this page provides verified electrical specifications, SC70 package layout, CML output interface details, and real-world use cases including pulse-width modulation and threshold detection in ATE and instrumentation.
Technical Context
The ADCMP606BKSZ-R2 uses Analog Devices' XFCB2 process to achieve ultra-low propagation delay dispersion (<2.3 ns over 10–125 mV overdrive) and robust input stage protection against large overdrive without phase reversal. Its fully back-matched CML output drives 50 Ω loads directly with 300–500 mV differential swing referenced to VCCO.
It features rail-to-rail input operation with dual-front-end crossover bias points at ~0.6 V and ~1.6 V, enabling stable performance across full common-mode range. Input offset voltage is ±5 mV max, and power supply rejection exceeds 60 dB - critical for noise-sensitive high-speed data acquisition paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Propagation Delay | 1.25 ns typical at 50 mV overdrive - enables <1 ns timing resolution in clock recovery and trigger circuits. |
| RMS Random Jitter | 2 ps at 200 mV overdrive, 0.5 V/ns slew - ensures sub-picosecond timing stability in serial data sampling. |
| Input Common-Mode Range | −0.2 V to VCCI + 0.2 V - supports ground-referenced and level-shifted inputs without external biasing. |
| CML Output Swing | 300–500 mV differential into 50 Ω terminated to VCCO - directly interfaces with FPGA transceivers and SERDES PHYs. |
| Supply Voltage Range | 2.5 V to 5.5 V single supply - simplifies power architecture in mixed-voltage systems (e.g., 3.3 V logic + 2.5 V analog rails). |
| Power Dissipation | 46 mW typical at 2.5 V - balances speed and thermal load in compact, high-density PCB layouts. |
| Operating Temperature | −40°C to +125°C - qualified for industrial and automotive under-hood applications requiring extended thermal reliability. |
Pinout & Package
ADCMP606BKSZ-R2 is housed in a 6-lead SC70 (KS-6) package with exposed pad not electrically connected; pin 2 (VEE) serves as the negative supply reference and thermal path. The package measures 2.00 mm × 1.25 mm × 0.90 mm and is JEDEC MO-203-AB compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (Q) | Noninverting Output | CML output sourcing/sinking current; logic high when VP > VN; requires 50 Ω termination to VCCO. |
| 2 (VEE) | Negative Supply / Ground Reference | Common return for input and output stages; must be connected to system ground or negative rail. |
| 3 (VP) | Noninverting Analog Input | Rail-to-rail input accepting −0.2 V to VCCI + 0.2 V; low 1 pF capacitance minimizes loading on high-Z sources. |
| 4 (VN) | Inverting Analog Input | Matches VP in bandwidth and common-mode range; differential pair enables precise threshold comparison. |
| 5 (VCCI/VCCO) | Shared Input/Output Supply | Single-pin supply for both sections; sets input common-mode range and output swing reference. |
| 6 (Q) | Inverting Output | Complementary CML output; 180° phase opposite Q; enables differential signaling without external inverters. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail input operation | Valid down to −0.2 V and up to VCCI + 0.2 V - eliminates need for external level-shifting networks in DC-coupled paths. |
| CML-compatible back-matched outputs | Integrated 50 Ω series termination enables direct 50 Ω transmission line driving - reduces board-level reflections and jitter. |
| Low propagation delay dispersion | <2.3 ns variation over 10–125 mV overdrive - preserves pulse width integrity in time-of-flight and spectroscopy applications. |
| Robust input overdrive tolerance | No phase reversal beyond valid input range - prevents false triggering during transient surges or ESD events. |
| High PSRR (>60 dB) | Maintains timing accuracy despite supply ripple - critical for shared power domains with switching regulators or digital noise. |
Applications
| High-Speed Clock Recovery | Threshold Detection in ATE |
|---|---|
Use Scenario: Restoring degraded clock signals from long PCB traces or backplanes in FPGA-based test equipment. IC Role / Device Role / Timing Role: Comparator acting as a self-biased slicer with 50% duty cycle preservation and sub-ns edge alignment. Use Value: Enables reliable 1+ GHz clock retiming without external hysteresis or bias resistors due to rail-to-rail input and CML output compatibility. |
Use Scenario: Detecting voltage thresholds on DUT power rails during functional testing with nanosecond response. IC Role / Device Role / Timing Role: High-speed comparator generating strobes synchronized to test pattern edges for capture timing validation. Use Value: Delivers 1.25 ns propagation delay and <2.3 ns overdrive dispersion - ensuring deterministic pass/fail decisions across varying signal amplitudes. |
| Pulse-Width Modulation Generator | Logic Level Translation |
Use Scenario: Building compact PWM oscillators using RC feedback and internal hysteresis-free comparison in motor control subsystems. IC Role / Device Role / Timing Role: Core timing element comparing ramp voltage against fixed reference to generate variable-duty-cycle outputs. Use Value: Achieves stable 1.1 ns minimum pulse width at 5.5 V supply - supports >900 MHz PWM carrier frequencies with minimal dead-time uncertainty. |
Use Scenario: Converting LVDS or PECL logic levels to CML-compatible signals for interfacing between legacy and modern SerDes ICs. IC Role / Device Role / Timing Role: Bidirectional level shifter preserving signal integrity via matched rise/fall times (160 ps) and low skew (20 ps Q-to-Q). Use Value: Eliminates external termination networks by integrating back-matched CML drivers - reducing component count and layout complexity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed comparator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADCMP607BKSZ-REEL7 | 12-lead LFCSP with split VCCI/VCCO supplies, latch/hysteresis control pin, and shutdown - no shared supply pin. | Required for designs needing independent input/output voltage control or programmable hysteresis/latch functionality. | Select ADCMP607BKSZ-REEL7 only if dual-supply operation, latch mode, or hysteresis adjustment is mandatory; otherwise ADCMP606BKSZ-R2 offers smaller footprint and simpler biasing. |
| TLV3501DBVR | 3.3 V–5.5 V supply, 4.5 ns propagation delay, CMOS output, no CML interface - higher jitter (15 ps RMS), no rail-to-rail input. | Suitable for cost-sensitive, lower-speed applications where CML compatibility and sub-ns timing are not required. | Choose TLV3501DBVR only for non-critical timing paths below 250 MHz; ADCMP606BKSZ-R2 remains superior for >500 MHz clock/data restoration. |
Compared with ADCMP606BKSZ-R2, ADCMP607BKSZ-REEL7 adds functional flexibility at the cost of larger package and more complex supply routing, while TLV3501DBVR trades speed and interface fidelity for lower cost and broader availability - making ADCMP606BKSZ-R2 the optimal choice for space-constrained, high-fidelity CML signal conditioning.
Availability
ADCMP606BKSZ-R2 is available at Aetrix Electronics and suitable for high-speed clock recovery, automatic test equipment (ATE), and pulse spectroscopy requiring stable component supply with guaranteed long-term manufacturability.
Supply support for ADCMP606BKSZ-R2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design and manufacturing expertise spanning precision, power, and high-speed signal chains.
The ADCMP606BKSZ-R2 belongs to Analog Devices' high-speed comparator product line, engineered specifically for sub-nanosecond timing applications in instrumentation, communications infrastructure, and automated test systems where jitter, delay, and interface compatibility are critical.
FAQ
What is the maximum input overdrive the ADCMP606BKSZ-R2 can tolerate without phase reversal?
The ADCMP606BKSZ-R2 input stage is designed to prevent phase reversal even when inputs exceed the valid common-mode range. Per the datasheet, it tolerates input voltages from −0.5 V to VCCI + 0.5 V without output inversion - a key reliability feature for systems exposed to transient overvoltage events. This behavior is confirmed across −40°C to +125°C operation.
Does the ADCMP606BKSZ-R2 require external termination resistors for CML output operation?
No, the ADCMP606BKSZ-R2 integrates back-matched 50 Ω series termination on both Q and Q outputs. When driving a 50 Ω transmission line referenced to VCCO, no external resistors are needed - simplifying layout and minimizing signal reflections. External termination is only required if interfacing with non-50 Ω loads or different reference voltages.
Can the ADCMP606BKSZ-R2 operate with separate input and output supply voltages?
No - the ADCMP606BKSZ-R2 uses a single shared supply pin (VCCI/VCCO) for both input and output sections. For split-supply operation with independent VCCI and VCCO, the pin-compatible ADCMP607BKSZ-REEL7 must be used instead. This architectural difference is fundamental to the ADCMP606BKSZ-R2's compact SC70 footprint.
What is the minimum pulse width the ADCMP606BKSZ-R2 can reliably detect at 5.5 V supply?
At VCCI = VCCO = 5.5 V, the ADCMP606BKSZ-R2 supports a minimum input pulse width of 1.1 ns while maintaining 90% output fidelity (PWMIN specification). This enables accurate detection of narrow glitches and fast transient events in high-bandwidth monitoring circuits, provided proper PCB layout and bypassing are implemented.
Is the ADCMP606BKSZ-R2 RoHS compliant and lead-free?
Yes - the ADCMP606BKSZ-R2 is manufactured in a RoHS-compliant, lead-free process and meets JEDEC standard MO-203-AB for the SC70 package. The "BKSZ" suffix denotes lead-free, halogen-free, and green-compliant packaging per Analog Devices' environmental policy, with full compliance documentation available through authorized distributors.
ADCMP606BKSZ-R2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Type:
- General Purpose
- Number of Elements:
- 1
- Output Type:
- CML
- Voltage - Supply, Single/Dual (±):
- 2.5V ~ 5.5V
- :
- 5mV @ 2.5V
- Voltage - Input Offset (Max):
- 5µA @ 2.5V
- Current - Input Bias (Max):
- 50mA
- Current - Output (Typ):
- 26mA
- Current - Quiescent (Max):
- 50dB CMRR, 50dB PSRR
- CMRR, PSRR (Typ):
- 2.1ns
- Propagation Delay (Max):
- 100µV
- Hysteresis:
- -40°C ~ 125°C
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- Surface Mount
- :
- SC-70-6
ADCMP606BKSZ-R2 FAQ
1.How can I place an order for ADCMP606BKSZ-R2 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADCMP606BKSZ-R2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADCMP606BKSZ-R2 reliable?
The price and inventory of ADCMP606BKSZ-R2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADCMP606BKSZ-R2 is usually 5 days.
3.What payment methods are accepted for ADCMP606BKSZ-R2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADCMP606BKSZ-R2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADCMP606BKSZ-R2?
ADCMP606BKSZ-R2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADCMP606BKSZ-R2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADCMP606BKSZ-R2?
For technical support, including ADCMP606BKSZ-R2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADCMP606BKSZ-R2 requirements.
6.How does Aetrix verify that ADCMP606BKSZ-R2 is sourced from the original manufacturer or authorized distributors?
All ADCMP606BKSZ-R2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADCMP606BKSZ-R2 meets industry standards.
7.What is the process for return or replacement of ADCMP606BKSZ-R2?
All ADCMP606BKSZ-R2 units undergo pre-shipment inspection (PSI). If there is an issue with ADCMP606BKSZ-R2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADCMP606BKSZ-R2 part is unused and in its original packaging.
Return procedure for ADCMP606BKSZ-R2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADCMP606BKSZ-R2 Tags

-
LM2903DR
Texas Instruments
-
LM339DR
Texas Instruments

-
LM339PWR
Texas Instruments

-
LM393DT
STMicroelectronics

-
LM2901PWR
Texas Instruments

-
LM2903DT
STMicroelectronics

-
LM393DR
Texas Instruments
-
LM239DR
Texas Instruments

-
LM339APWR
Texas Instruments

-
LM2903P
Texas Instruments

-
LM393ADR
Texas Instruments

-
NCX2200GMAZ
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

