Analog Devices Inc. ADD8754DACPZ-REEL7
- Part No.:
- ADD8754DACPZ-REEL7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 24-VFQFN Exposed Pad, CSP
- Datasheet:
-
ADD8754DACPZ-REEL7.pdf
- Description:
- IC CONV DC/DC STEPUP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADD8754DACPZ-REEL7 from Analog Devices is a highly integrated TFT LCD panel power management IC featuring a 2 A step-up switching regulator (up to 20 V), 350 mA logic LDO with selectable 2.5 V/2.85 V/3.3 V outputs, 300 mA VCOM amplifier, and gate pulse modulation circuitry - all in a single 24-lead LFCSP package. It delivers complete panel biasing for monitors, notebooks, and TVs with minimal external components.
For engineers reviewing the ADD8754DACPZ-REEL7 datasheet, ADD8754DACPZ-REEL7 pinout, ADD8754DACPZ-REEL7 application, or ADD8754DACPZ-REEL7 equivalent, key selection criteria include VCOM drive capability (±300 mA), dual-frequency step-up regulator (650 kHz / 1.2 MHz), independent gate pulse delay/slope control, and industrial temperature range (−40°C to +85°C) compliance.
Technical Context
The ADD8754DACPZ-REEL7 integrates four functionally distinct subsystems: a current-mode step-up DC/DC converter with internal 2 A switch and soft-start; a triple-output LDO regulator with 300 mV dropout at 350 mA; a rail-to-rail VCOM amplifier optimized for capacitive TFT loads; and a gate pulse modulator with independently adjustable delay (via CE capacitor) and falling slope (via RE resistor). All share common ground domains (AGND/PGND/GND) but maintain separate supply paths for noise isolation.
Its functional block diagram confirms strict signal-domain separation: VIN_1/VIN_2 feed LDO and boost stages separately; VDD_1 powers gate modulation logic; VDD_2 supplies the VCOM amplifier; and OUT serves as both VCOM amplifier output and VDD_2 reference. The FREQ pin selects switching frequency without changing regulation loop compensation requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Step-up Output Range | Adjustable up to 20 V - supports VGH generation for large-format TFT panels requiring high gate drive voltage. |
| LDO Output Options | Selectable 2.5 V / 2.85 V / 3.3 V - enables compatibility with multiple logic families (TTL, LVCMOS, SSTL) on same panel. |
| VCOM Drive Current | ±300 mA peak - sustains stable VCOM voltage under fast frame-rate transitions and high-resolution pixel loading. |
| Gate Pulse Delay Control | 1.88 μs typical (CE = 470 pF, RE = 33 kΩ) - fine-tunes gate-on timing to suppress crosstalk and improve image uniformity. |
| Switching Frequency | 650 kHz or 1.2 MHz - allows trade-off between EMI filtering complexity (lower freq) and external component size (higher freq). |
| Operating Temperature | −40°C to +85°C - validated for industrial-grade display modules used in commercial monitors and embedded HMI systems. |
| Package | 24-lead, 4 mm × 4 mm, Pb-free LFCSP - provides low thermal resistance (θJA = 38°C/W) and compact footprint for space-constrained display PCBs. |
Pinout & Package
ADD8754DACPZ-REEL7 uses a 24-lead, 4 mm × 4 mm, Pb-free LFCSP package with exposed thermal pad (pin 21 = PGND). Pin functions are electrically and thermally segregated: VIN_1/VIN_2 supply inputs, LX is high-side switch node, VGH_M is gate modulation output, POS/NEG define VCOM amplifier differential input, and ADJ selects LDO output voltage via resistor configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 GND | System Ground Reference | Common return for analog, power, and digital sections - must be connected to low-impedance ground plane. |
| 2 VGH_M | Gate Pulse Modulator Output | Drives TFT gate line after modulation; requires external RC network (RE/CE) for slope/delay tuning. |
| 3 VFLK | Gate Pulse Trigger Input | Edge-sensitive control that initiates gate pulse shaping sequence when voltage exceeds 2.2 V. |
| 4 VDPM | Gate Pulse Enable | Logic-level enable for VGH_M output - disables gate drive when pulled low. |
| 7 OUT | VCOM Amplifier Output | High-current output driving LCD VCOM plane; capable of ±300 mA into capacitive load. |
| 8 NEG / 9 POS | VCOM Amplifier Inputs | Differential input pair setting VCOM reference voltage; POS accepts DC bias, NEG connects to feedback point. |
| 11 ADJ | LDO Voltage Select | Three-state pin (GND/OPEN/LDO_OUT) configures LDO output to 3.3 V / 2.85 V / 2.5 V respectively. |
| 13 VIN_1 | LDO & Boost Input | Primary supply for LDO regulator and step-up controller - must be 3.0–5.5 V with low-ESR bypass. |
| 16 FREQ | Switching Frequency Select | GND = 650 kHz, VIN_1 = 1.2 MHz - sets oscillator without altering loop compensation design. |
| 18 LX | Boost Switch Node | Connects to external inductor and Schottky diode; carries high di/dt - requires short, wide trace routing. |
| 19 SHDN | Global Shutdown Control | Pull low to disable all regulators and amplifiers; quiescent current drops to 2.0 μA. |
| 20 FB | Boost Output Feedback | Senses regulated output via resistive divider; internal 1.211 V reference enables precise VOUT programming. |
| 21 PGND | Power Ground | High-current return path for boost switch and gate driver - isolated from AGND to minimize noise coupling. |
| 22 CE | Gate Delay Capacitor | Capacitor to GND sets delay time (TDELAY = CE × 4200); 470 pF yields ~1.98 μs typical delay. |
| 23 RE | Gate Fall Slope Resistor | Resistor to GND sets discharge rate (IVGH_M = 302.5/(RE + 5000)); 33 kΩ yields ~8.0 mA sink current. |
| 24 VGH | High-Voltage Gate Input | Accepts external high-voltage source (7–30 V) for gate pulse modulation - not generated internally. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated VCOM Amplifier | 300 mA peak drive with 105 V/μs slew rate - eliminates need for discrete op-amp and external buffer stage. |
| Programmable Gate Pulse Shape | Independent delay (CE) and falling slope (RE) control - reduces vertical line flicker and improves grayscale fidelity. |
| Dual-Frequency Step-Up Regulator | 650 kHz (high efficiency) or 1.2 MHz (smaller magnetics) - enables layout optimization without redesigning compensation network. |
| Triple-Output LDO | 2.5 V / 2.85 V / 3.3 V selectable via ADJ pin - supports mixed-voltage logic interfaces on single display interface (e.g., LVDS + GPIO). |
| Soft-Start Protection | 2.5 μA internal current source charges SS pin capacitor - limits inrush current during panel power-up to prevent supply sag. |
| Thermal & UVLO Protection | 125°C junction limit and 2.6 V/2.8 V UVLO thresholds - ensures safe operation during cold start or brownout conditions. |
Applications
| Monitor Panel Power Supply | Notebook Display Biasing |
|---|---|
Use Scenario: Driving 24-inch WXGA TFT panel requiring VGH = 20 V, VGL = −7 V, VCOM = 5.2 V, and 3.3 V logic rails. IC Role / Device Role / Timing Role: Single-chip panel power manager generating all bias voltages and modulating gate pulses to suppress crosstalk. Use Value: Reduces BOM count by 7 discrete regulators/amplifiers; enables <10 ms power-up sequencing per JEIDA standard. |
Use Scenario: Powering 15.6-inch FHD IPS panel in ultrabook with tight thermal envelope and EMI constraints. IC Role / Device Role / Timing Role: Provides VCOM stabilization and gate pulse shaping while operating at 1.2 MHz to shrink inductor size. Use Value: Achieves 93% boost efficiency at 150 mA load; meets FCC Class B radiated emissions with minimal filtering. |
| Industrial HMI Display | Medical Imaging Monitor |
Use Scenario: Operating in factory environment with −40°C startup and 85°C ambient, powering 10.1-inch resistive touch panel. IC Role / Device Role / Timing Role: Delivers robust VCOM drive and gate modulation across full industrial temperature range with no derating. Use Value: Maintains <±10 mV VCOM drift over temperature - critical for consistent grayscale reproduction in control panels. |
Use Scenario: Supporting diagnostic-grade 2MP monochrome display requiring zero image lag and artifact-free grayscale transitions. IC Role / Device Role / Timing Role: Precisely shapes gate pulses to eliminate vertical banding and ensures VCOM settling within 1.5 μs after frame sync. Use Value: Enables <50 ns gate pulse edge jitter - meets DICOM Part 14 luminance uniformity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TFT LCD panel power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65105RGER | Single 300 mA LDO; no VCOM amplifier; gate modulation limited to fixed delay only. | Suitable for smaller panels (<12") with simpler timing requirements; lacks independent slope control. | Choose when cost sensitivity outweighs VCOM drive strength and gate pulse flexibility. |
| MAX1664ETM+ | Separate VCOM buffer (MAX4426) required; no integrated gate pulse modulator; 1.5 A boost switch. | Requires additional ICs for full functionality; better suited for legacy designs with existing MAXIM ecosystem. | Prefer when upgrading from older MAX166x family and board space permits multi-chip solution. |
Compared with TPS65105RGER and MAX1664ETM+, the ADD8754DACPZ-REEL7 uniquely integrates VCOM drive, programmable gate pulse shaping, and triple-LDO output in one package - reducing total solution size by 40% and eliminating inter-IC timing skew in high-resolution displays.
Availability
ADD8754DACPZ-REEL7 is available at Aetrix Electronics and suitable for TFT LCD monitor power supplies, notebook display biasing, and industrial HMI panel designs requiring stable component supply, long-term lifecycle support, and guaranteed Pb-free compliance.
Supply support for ADD8754DACPZ-REEL7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and ISO 9001-certified manufacturing.
The ADD8754 belongs to Analog Devices' Display Power Management product line, engineered specifically for single-chip TFT LCD panel biasing - targeting reduced system cost, improved image quality, and simplified design for commercial and industrial displays.
FAQ
What is the maximum output voltage supported by the step-up regulator in ADD8754DACPZ-REEL7?
The ADD8754DACPZ-REEL7 step-up switching regulator supports an adjustable output voltage up to 20 V, set via the FB pin using a resistive divider. This enables direct generation of VGH for large-format TFT panels without external boost stages. The internal 2 A power switch and 93% peak efficiency ensure stable high-voltage operation under full load.
How does the ADD8754DACPZ-REEL7 configure its LDO output voltage?
The ADD8754DACPZ-REEL7 configures its LDO output voltage through the ADJ pin: connecting ADJ to GND selects 3.3 V, leaving it open selects 2.85 V, and tying it to LDO_OUT selects 2.5 V. Each option maintains ±3% accuracy across −40°C to +85°C and delivers up to 350 mA with 300–500 mV dropout voltage.
Can the VCOM amplifier in ADD8754DACPZ-REEL7 drive high-capacitance LCD panels?
Yes - the ADD8754DACPZ-REEL7 VCOM amplifier delivers ±300 mA peak current with 105 V/μs slew rate and is explicitly designed for high-capacitance TFT panel loads. Its architecture ensures stable operation with >1 μF effective VCOM capacitance, meeting timing requirements for 120 Hz refresh rates and WQXGA resolution.
What external components are required to set gate pulse delay and falling slope in ADD8754DACPZ-REEL7?
Gate pulse delay is set by capacitor CE (e.g., 470 pF for ~1.88 μs), connected between pin 22 (CE) and GND. Falling slope is controlled by resistor RE (e.g., 33 kΩ for ~8.0 mA discharge current), connected between pin 23 (RE) and GND. These values are calculated per datasheet equations: TDELAY = CE × 4200 and IVGH_M = 302.5/(RE + 5000).
Does ADD8754DACPZ-REEL7 support shutdown mode, and what is its quiescent current?
Yes - ADD8754DACPZ-REEL7 supports full system shutdown via the SHDN pin (pin 19). When pulled low, it disables all regulators and amplifiers, reducing total ground current to 2.0 μA. This enables ultra-low-power standby states in battery-backed displays and portable medical monitors.
ADD8754DACPZ-REEL7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- ADD8754
- Package/Case:
- 24-VFQFN Exposed Pad, CSP
- Packaging:
- Bulk
- Product Status:
- Active
- Applications:
- -
- Voltage - Input:
- -
- Number of Outputs:
- -
- Voltage - Output:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-LFCSP-VQ (4x4)
ADD8754DACPZ-REEL7 FAQ
1.How can I place an order for ADD8754DACPZ-REEL7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADD8754DACPZ-REEL7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADD8754DACPZ-REEL7 reliable?
The price and inventory of ADD8754DACPZ-REEL7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADD8754DACPZ-REEL7 is usually 5 days.
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Once your ADD8754DACPZ-REEL7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADD8754DACPZ-REEL7?
For technical support, including ADD8754DACPZ-REEL7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADD8754DACPZ-REEL7 requirements.
6.How does Aetrix verify that ADD8754DACPZ-REEL7 is sourced from the original manufacturer or authorized distributors?
All ADD8754DACPZ-REEL7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADD8754DACPZ-REEL7 meets industry standards.
7.What is the process for return or replacement of ADD8754DACPZ-REEL7?
All ADD8754DACPZ-REEL7 units undergo pre-shipment inspection (PSI). If there is an issue with ADD8754DACPZ-REEL7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADD8754DACPZ-REEL7 part is unused and in its original packaging.
Return procedure for ADD8754DACPZ-REEL7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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