Analog Devices Inc. ADF4106BCP-REEL7
- Part No.:
- ADF4106BCP-REEL7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADF4106BCP-REEL7.pdf
- Description:
- IC PLL FREQ SYNTHESIZER 20-LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:13,500
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADF4106BCP-REEL7 from Analog Devices is a 6 GHz integer-N PLL frequency synthesizer IC used as a local oscillator in RF up/down-conversion stages. It integrates a phase-frequency detector (PFD), precision charge pump, dual-modulus prescaler (8/9, 16/17, 32/33, 64/65), 13-bit B counter, 6-bit A counter, and 14-bit R counter. Operates from 2.7 V to 3.3 V with separate VP supply up to 5.5 V, enabling extended tuning voltage in 3 V systems - critical for broadband wireless transceivers.
For engineers reviewing the ADF4106BCP-REEL7 datasheet, ADF4106BCP-REEL7 pinout, ADF4106BCP-REEL7 application, or ADF4106BCP-REEL7 equivalent, this page delivers verified technical context, real-world design meaning of key specs, validated pin functions, confirmed application roles, and two rigorously cross-checked alternative parts - all grounded in Analog Devices' Rev. F datasheet and LFCSP package documentation.
Technical Context
The ADF4106BCP-REEL7 implements an N-divider architecture where N = BP + A, using a synchronous 4/5-core dual-modulus prescaler programmable via serial interface. Its PFD supports up to 104 MHz phase detector frequency and includes programmable antibacklash pulse width (ABP1/ABP2 bits) to eliminate dead zone and suppress reference spurs.
Charge pump current is set by external RSET (3.0–11 kΩ), delivering 625 µA (low) or 5 mA (high) with ±2% matching and <2 nA three-state leakage. MUXOUT provides selectable access to lock detect (digital/analog), scaled RF, or scaled reference - configurable via M3/M2/M1 bits in the function latch.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Input Frequency | 0.5–6.0 GHz: Enables direct synthesis without frequency doublers in LMDS, satellite, and 5G base station LO paths. |
| Phase Detector Frequency | Up to 104 MHz: Supports high PFD rates for fast lock time and wide loop bandwidth (e.g., 100 kHz at 5.8 GHz). |
| Charge Pump Current | 625 µA or 5 mA (programmable): Matches loop filter impedance requirements across VCO gain ranges (e.g., 5 mA for high-KVCO VCOs). |
| Reference Input Range | 20–300 MHz: Accepts crystal oscillators or divided clocks; AC-coupled with AVDD/2 bias for robust noise immunity. |
| Power Supply | AVDD/DVDD = 2.7–3.3 V; VP = AVDD to 5.5 V: Separates analog charge pump rail to extend VCO tuning voltage beyond 3 V supply. |
| Phase Noise Floor | –223 dBc/Hz (normalized): Enables low in-band jitter in instrumentation and wireless LAN local oscillators. |
| Lock Detect | Digital (3- or 5-cycle threshold) and analog (open-drain): Provides system-level PLL status monitoring with configurable response latency. |
Pinout & Package
ADF4106BCP-REEL7 is packaged in a 20-lead LFCSP_WQ (4 mm × 4 mm, 0.5 mm pitch) with exposed paddle soldered to AGND. Pin numbering follows top-view layout per Figure 4 of Rev. F datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RSET | Charge pump current setting | Connects external resistor (e.g., 5.1 kΩ) to CPGND to set ICP = 5 mA; nominal voltage = 0.66 V. |
| CP | Charge pump output | Drives external loop filter; requires decoupling to CPGND; VP ≥ AVDD ensures full tuning range. |
| CPGND | Charge pump ground return | Dedicated low-noise ground path for CP; must be isolated from digital DGND to minimize coupling. |
| RFINA / RFINB | Differential RF input | AC-coupled inputs to prescaler; RFINA accepts small-signal VCO output; RFINB is complementary (±600 mV max diff). |
| REFIN | Reference clock input | CMOS input biased at AVDD/2; accepts 20–300 MHz TTL/CMOS or AC-coupled sources; 100 kΩ input resistance. |
| CLK / DATA / LE | 3-wire serial interface | 24-bit shift register control: CLK rising edge latches DATA (MSB first); LE rising edge loads into selected latch (R/N/Function/Init). |
| MUXOUT | Multiplexer output | Selectable via M3/M2/M1: digital lock detect, analog lock detect, scaled RF, or scaled REFIN - enables debug and system monitoring. |
| CE | Chip enable | Active-low hardware power-down; places CP in three-state and reduces IDD to 10 µA typical. |
| VP | Charge pump supply | Independent rail (≥AVDD, ≤5.5 V); allows 5 V tuning voltage in 3 V systems - essential for wide-Vtune VCOs. |
Key Features
| Feature | Design Value |
|---|---|
| 6 GHz RF input bandwidth | Eliminates need for frequency doublers in 5.8 GHz wireless LAN and LMDS base station transmitters, reducing BOM count and board area. |
| Separate VP supply (up to 5.5 V) | Extends VCO tuning range beyond 3 V supply rails - critical for high-performance VCOs requiring >3.3 V tuning voltage. |
| Programmable dual-modulus prescaler | Four selectable ratios (8/9, 16/17, 32/33, 64/65) enable contiguous frequency coverage across wide bands without gaps or re-tuning. |
| Programmable antibacklash pulse width | Configurable ABP1/ABP2 bits eliminate PFD dead zone, directly reducing reference spurs and in-band phase noise. |
| Analog and digital lock detect | Dual lock outputs support both microcontroller GPIO polling (digital) and analog comparator monitoring (analog), improving system diagnostics. |
Applications
| Wireless LAN Transmitter LO | Satellite Uplink Local Oscillator |
|---|---|
|
Use Scenario: Generating 5.15–5.825 GHz LO for IEEE 802.11a/n/ac WLAN transmitters with tight EVM and spectral mask compliance. IC Role / Device Role / Timing Role: Integer-N PLL synthesizer providing stable, low-phase-noise LO signal synchronized to 40 MHz reference clock. Use Value: –76.5 dBc/Hz phase noise @ 1 kHz offset at 5.8 GHz enables <–30 dB EVM under 802.11ac 256-QAM modulation. |
Use Scenario: Local oscillator in Ka-band satellite uplink transmitters requiring frequency agility and low spurious emissions. IC Role / Device Role / Timing Role: High-bandwidth PLL core driving external VCO; R counter divides 100 MHz OCXO to 1 MHz PFD frequency. Use Value: 6 GHz RF input capability supports direct synthesis up to 26.5 GHz with x4 multiplier, avoiding cascaded PLL complexity. |
| LMDS Base Station Transmitter | Test & Measurement Instrumentation LO |
|
Use Scenario: 24–26 GHz LMDS base station transmitter requiring rapid frequency hopping and low close-in phase noise. IC Role / Device Role / Timing Role: Programmable N-divider generating 12–13 GHz IF LO; dual-modulus prescaler (32/33) enables 100 kHz channel spacing. Use Value: 104 MHz max PFD frequency allows 200 kHz loop bandwidth for <100 µs lock time during frequency hop sequences. |
Use Scenario: Frequency-agile LO source in spectrum analyzers and signal generators demanding ultra-low phase noise and spurious performance. IC Role / Device Role / Timing Role: Reference-grade PLL synthesizer locked to 10 MHz atomic clock; MUXOUT monitors analog lock detect for calibration stability. Use Value: –223 dBc/Hz normalized phase noise floor and –122 dBc/Hz 1/f noise ensure <0.36° RMS integrated jitter at 900 MHz carrier. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADF4153ACPZ-R7 | Higher max RF input (6.5 GHz), integrated LDO, but no separate VP supply; 24-lead LFCSP. | Lacks VP rail flexibility - cannot drive VCOs requiring >3.3 V tuning voltage without external regulator. | Choose when system uses single 3.3 V rail and prioritizes integration over tuning voltage headroom. |
| LMX2531LQ1770E/NOPB | Fractional-N architecture, 2.6 GHz max RF input, integrated VCO, SPI interface; QFN-32 package. | Lower RF bandwidth limits use to sub-3 GHz applications; integrated VCO removes external component but reduces design flexibility. | Choose for compact, lower-frequency designs where fractional-N resolution and smaller footprint outweigh 6 GHz capability. |
Compared with ADF4106BCP-REEL7, ADF4153ACPZ-R7 trades VP flexibility for on-chip regulation and higher RF limit, while LMX2531LQ1770E/NOPB sacrifices RF bandwidth and external VCO control for fractional-N resolution and integration - making ADF4106BCP-REEL7 optimal for 6 GHz integer-N systems needing extended tuning voltage.
Availability
ADF4106BCP-REEL7 is available at Aetrix Electronics and suitable for broadband wireless access infrastructure, satellite communication terminals, and RF test equipment requiring stable component supply and long-term industrial availability.
Supply support for ADF4106BCP-REEL7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and RF ICs, headquartered in Norwood, MA, with design centers worldwide and manufacturing in the U.S., Ireland, and the Philippines.
The ADF4106 belongs to Analog Devices' precision PLL synthesizer product line, engineered for RF local oscillator generation in wireless infrastructure, aerospace, and instrumentation - emphasizing low phase noise, wide bandwidth, and flexible power architecture.
FAQ
What is the maximum RF input frequency supported by the ADF4106BCP-REEL7?
The ADF4106BCP-REEL7 supports an RF input frequency range of 0.5 GHz to 6.0 GHz, as specified in Table 1 of the Rev. F datasheet. This 6 GHz bandwidth enables direct synthesis in LMDS, 5G FR1, and satellite uplink applications without requiring frequency multipliers - simplifying RF front-end design and improving system phase noise performance.
Does the ADF4106BCP-REEL7 require an external loop filter?
Yes, the ADF4106BCP-REEL7 requires an external passive loop filter between the CP pin and the tuning port of an external VCO. The charge pump output drives this filter to generate the VCO control voltage; loop filter design depends on desired bandwidth, phase margin, and VCO gain - no internal filter is integrated.
How is charge pump current configured on the ADF4106BCP-REEL7?
Charge pump current on the ADF4106BCP-REEL7 is set by an external resistor connected between RSET and CPGND. With RSET = 5.1 kΩ, the high-current setting yields 5 mA (typical); the low setting gives 625 µA. Current value is selected via CPI1–CPI6 bits in the function latch, and accuracy is ±2.5% with RSET = 5.1 kΩ.
What package type is used for the ADF4106BCP-REEL7?
The ADF4106BCP-REEL7 uses a 20-lead LFCSP_WQ package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Per Figure 4 and Table 4 of the Rev. F datasheet, the exposed pad must be soldered to AGND for thermal and electrical performance - distinct from the 16-lead TSSOP variant (ADF4106BRUZ).
Can the ADF4106BCP-REEL7 operate with a 2.5 V supply?
No - the ADF4106BCP-REEL7 specifies AVDD and DVDD minimum of 2.7 V per Table 1 (Rev. F). Operation below 2.7 V violates absolute maximum ratings and may cause functional failure or degraded phase noise and lock detect reliability. Systems requiring 2.5 V rails must select alternate synthesizers like ADF4158.
ADF4106BCP-REEL7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- *
- Package/Case:
- 20-WFQFN Exposed Pad, CSP
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF)
- PLL:
- Yes
- Input:
- CMOS
- Output:
- Clock
- Number of Circuits:
- -
- Ratio - Input:Output:
- 2:1
- Differential - Input:Output:
- Yes/No
- Frequency - Max:
- 6GHz
- Divider/Multiplier:
- No/No
- Voltage - Supply:
- 2.7V ~ 3.3V
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-LFCSP (4x4)
ADF4106BCP-REEL7 FAQ
1.How can I place an order for ADF4106BCP-REEL7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADF4106BCP-REEL7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADF4106BCP-REEL7 reliable?
The price and inventory of ADF4106BCP-REEL7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADF4106BCP-REEL7 is usually 5 days.
3.What payment methods are accepted for ADF4106BCP-REEL7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADF4106BCP-REEL7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADF4106BCP-REEL7?
ADF4106BCP-REEL7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADF4106BCP-REEL7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADF4106BCP-REEL7?
For technical support, including ADF4106BCP-REEL7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADF4106BCP-REEL7 requirements.
6.How does Aetrix verify that ADF4106BCP-REEL7 is sourced from the original manufacturer or authorized distributors?
All ADF4106BCP-REEL7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADF4106BCP-REEL7 meets industry standards.
7.What is the process for return or replacement of ADF4106BCP-REEL7?
All ADF4106BCP-REEL7 units undergo pre-shipment inspection (PSI). If there is an issue with ADF4106BCP-REEL7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADF4106BCP-REEL7 part is unused and in its original packaging.
Return procedure for ADF4106BCP-REEL7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADF4106BCP-REEL7 Tags
-
CD74HCT4046AM96
Texas Instruments

-
MC14046BDWR2G
onsemi

-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments

-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.

-
CY2305SXI-1T
Infineon Technologies

-
570BILFT
Renesas

-
CDCE913PWR
Texas Instruments

-
CY2305SXI-1HT
Infineon Technologies

-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

