Analog Devices Inc. ADF4106BCPZ-RL
- Part No.:
- ADF4106BCPZ-RL
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADF4106BCPZ-RL.pdf
- Description:
- IC CLK/FREQ SYNTH 20LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:3,765
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADF4106BCPZ-RL from Analog Devices is a 6 GHz PLL frequency synthesizer IC used as a local oscillator in RF up/down-conversion stages. It features dual-modulus prescaling (8/9, 16/17, 32/33, 64/65), programmable charge pump current (625 µA to 5 mA), separate VP supply for extended tuning voltage, and analog/digital lock detect - enabling high-frequency wireless base station transceivers with no frequency doubler required.
For engineers reviewing the ADF4106BCPZ-RL datasheet, ADF4106BCPZ-RL pinout, ADF4106BCPZ-RL application, or ADF4106BCPZ-RL equivalent, key selection criteria include its 6 GHz RF input capability, 20–300 MHz REFIN range, 3-wire serial interface timing (t1 ≥ 10 ns setup), and compatibility with external loop filters and VCOs in broadband wireless access and satellite systems.
Technical Context
The ADF4106BCPZ-RL implements an N-divider (N = BP + A) using a 13-bit B counter, 6-bit A counter, and programmable dual-modulus prescaler (P/P+1). Its phase frequency detector (PFD) supports up to 104 MHz phase detector frequency and includes programmable antibacklash pulse width (ABP1/ABP2 bits) to eliminate dead zone and suppress reference spurs.
It integrates separate analog (AVDD) and digital (DVDD) supplies (2.7–3.3 V), a dedicated charge pump supply (VP = AVDD to 5.5 V), and a 24-bit serial interface with LE/CLK/DATA control. The MUXOUT pin provides selectable access to lock detect, scaled RF, or scaled reference signals - critical for real-time PLL diagnostics in instrumentation and LMDS base stations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Input Frequency | 0.5–6.0 GHz: supports direct synthesis up to 6 GHz without frequency doublers, simplifying RF front-end architecture. |
| REFIN Frequency Range | 20–300 MHz: enables flexible reference clock sourcing from crystal oscillators or frequency dividers for diverse PFD rates. |
| Charge Pump Current | 625 µA–5 mA (programmable): sets loop filter bandwidth and transient response; configured via RSET (3.0–11 kΩ) and CPI bits. |
| Phase Detector Frequency | ≤104 MHz: determines maximum PFD rate; impacts reference spur level and loop stability in high-bandwidth PLL designs. |
| Power Supply | AVDD/DVDD = 2.7–3.3 V; VP = AVDD to 5.5 V: allows 5 V tuning voltage for wide-range VCOs while maintaining 3 V core logic. |
| Lock Detect | Analog (open-drain) and digital (CMOS) outputs: provides dual-mode PLL status monitoring for system-level fault detection and calibration. |
| Operating Temperature | –40°C to +85°C (Industrial B Version): qualified for deployment in outdoor wireless infrastructure and satellite terminal equipment. |
Pinout & Package
ADF4106BCPZ-RL is housed in a 20-lead LFCSP_WQ (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad soldered to AGND. Pin functions are validated per Analog Devices' Rev. F datasheet Figures 4 and Table 4.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RSET | Charge pump current setting | Resistor-to-ground sets ICP max (ICP = 25 V/RSET); 5.1 kΩ yields 5 mA for high-loop-gain applications. |
| CP | Charge pump output | Drives external loop filter; requires low-noise RC network to stabilize VCO tuning voltage and suppress ripple. |
| CPGND | Charge pump ground return | Must be isolated from digital ground to prevent noise coupling into sensitive analog feedback path. |
| RFINA / RFINB | Differential RF input | Accepts ac-coupled 50 Ω RF signal up to 6 GHz; RFINB requires 100 pF bypass to AGND per Figure 18. |
| REFIN | Reference clock input | CMOS input biased at AVDD/2; accepts 0.8–3.3 Vp-p signals; dc-coupled or ac-coupled with 100 kΩ termination. |
| CLK / DATA / LE | 3-wire serial interface | 24-bit MSB-first shift register; LE latches data to R/N/Function/Init latches based on C2/C1 control bits. |
| MUXOUT | Multiplexed diagnostic output | Selectable via M3/M2/M1: lock detect, divided RF, or divided REFIN - enables in-system PLL validation without probe access. |
| CE | Chip enable | Active-low hardware power-down; places CP in three-state and reduces IDD to 10 µA for standby mode. |
Key Features
| Feature | Design Value |
|---|---|
| 6 GHz RF input bandwidth | Eliminates need for frequency doublers in 5–6 GHz wireless LAN and LMDS systems, reducing component count and board area. |
| Separate VP supply (up to 5.5 V) | Enables full 0–5 V VCO tuning range in 3 V systems, supporting wide-kVCO oscillators without level-shifting circuitry. |
| Programmable dual-modulus prescaler | Four selectable ratios (8/9 to 64/65) allow optimal N-divider configuration for contiguous frequency coverage and minimal fractional spurs. |
| Antibacklash pulse width control | Configurable ABP1/ABP2 bits adjust PFD dead-zone compensation, directly reducing reference spurs and integrated phase noise. |
| Hardware/software power-down | CE pin (hardware) and F2 bit (software) independently disable internal blocks, achieving 10 µA quiescent current for battery-aware designs. |
Applications
| Wireless Base Station Transmitter | Satellite Communication Terminal |
|---|---|
Use Scenario: Local oscillator generation for 2.6 GHz LTE and 3.5 GHz 5G NR uplink transmission in macrocell base stations. IC Role / Device Role / Timing Role: PLL synthesizer generating stable, low-phase-noise LO signal locked to GPS-disciplined 10 MHz reference. Use Value: 6 GHz bandwidth and –76.5 dBc/Hz @ 1 kHz offset (5.8 GHz) ensure EVM compliance and adjacent channel leakage ratio (ACLR) margin. | Use Scenario: Frequency translation in Ka-band satellite modems operating at 26–40 GHz downlink bands. IC Role / Device Role / Timing Role: First-stage LO synthesizer driving active mixer; output feeds x2/x3 multiplier chain to reach final RF band. Use Value: Dual-modulus prescaler flexibility (32/33, 64/65) enables integer-N synthesis across wide IF ranges without fractional-N complexity or sigma-delta noise. |
| Broadband Wireless Access (LMDS) | Test & Measurement Instrumentation |
Use Scenario: LO source in 24–28 GHz fixed wireless access subscriber units for high-speed backhaul. IC Role / Device Role / Timing Role: High-frequency synthesizer providing agile, low-spur LO to direct-conversion receiver and transmitter paths. Use Value: Programmable charge pump current (625 µA–5 mA) allows optimization of loop bandwidth for fast frequency hopping (<100 µs settling) while maintaining stability. | Use Scenario: Reference source in spectrum analyzers and signal generators requiring ultra-low phase noise and rapid frequency switching. IC Role / Device Role / Timing Role: Core PLL engine generating tunable LO with sub-Hz resolution and <15 ns digital lock detect latency. Use Value: Analog and digital lock detect outputs enable closed-loop calibration routines and real-time PLL health monitoring during automated test sequences. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADF4153AACPZ-R7 | Integrated VCO (4.4–5.6 GHz); lower RF input max (5.6 GHz); no separate VP pin; higher typical phase noise floor (–219 dBc/Hz). | Best for compact, single-chip LO solutions where board space is constrained and VCO integration is acceptable. | Select ADF4153A when eliminating external VCO and loop filter saves cost/area, and 5.6 GHz max output suffices. |
| HMC703LP4E | Wider RF input (up to 13 GHz); higher PFD frequency (250 MHz); requires external LDO for 5 V VP rail; no analog lock detect. | Preferred for millimeter-wave test equipment and radar LOs demanding >6 GHz native synthesis and faster lock times. | Choose HMC703LP4E for >6 GHz direct synthesis or when 250 MHz PFD enables tighter loop bandwidths and lower integrated jitter. |
Compared with ADF4106BCPZ-RL, ADF4153A offers integration at the expense of frequency range and tuning flexibility, while HMC703LP4E extends bandwidth and speed but increases power and layout complexity - making ADF4106BCPZ-RL the balanced choice for 6 GHz wireless infrastructure with external VCO control.
Availability
ADF4106BCPZ-RL is available at Aetrix Electronics and suitable for broadband wireless access, satellite communication terminals, and instrumentation requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for ADF4106BCPZ-RL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and RF ICs, serving precision instrumentation, communications, and industrial markets since 1965.
The ADF4106 belongs to Analog Devices' PLL frequency synthesizer product line, designed specifically for high-frequency wireless infrastructure where low phase noise, wide RF bandwidth, and flexible prescaling are essential for carrier-grade LO generation.
FAQ
What is the maximum RF input frequency supported by the ADF4106BCPZ-RL?
The ADF4106BCPZ-RL supports an RF input frequency range of 0.5 GHz to 6.0 GHz, as specified in Table 1 of the Rev. F datasheet. This enables direct synthesis up to 6 GHz without requiring frequency multipliers, simplifying RF system architecture in LMDS and 5G base station applications. Operation below 0.5 GHz requires slew rate >320 V/µs to ensure proper prescaler triggering.
Does the ADF4106BCPZ-RL require an external loop filter?
Yes, the ADF4106BCPZ-RL requires an external passive loop filter between the CP pin and the VCO tuning input. The charge pump output drives this filter to generate the analog control voltage; filter design directly impacts PLL stability, lock time, and phase noise performance. Analog Devices provides ADIsimPLL software to model and optimize filter components for specific ADF4106BCPZ-RL configurations.
How is the charge pump current programmed on the ADF4106BCPZ-RL?
The ADF4106BCPZ-RL charge pump current is set via two independent methods: (1) analog scaling using an external RSET resistor (3.0–11 kΩ) tied to CPGND, yielding ICP = 25 V/RSET; and (2) digital scaling using six CPI bits (CPI1–CPI6) in the Function Latch to select one of 64 discrete current levels within the RSET-defined range. Both methods are documented in Table 9 and Figure 20 of the datasheet.
What package type is used for the ADF4106BCPZ-RL?
The ADF4106BCPZ-RL uses a 20-lead LFCSP_WQ (Lead Frame Chip Scale Package, wettable flank) measuring 4 mm × 4 mm with 0.5 mm pitch and an exposed thermal pad. Per Figure 4 and Package Outline Drawing CP-20-2, the exposed pad must be soldered to AGND for thermal and electrical performance. This differs from the TSSOP variant (ADF4106BRUZ) and is confirmed in the Ordering Guide (Page 22, Rev. F).
Can the ADF4106BCPZ-RL operate with a 3.3 V AVDD/DVDD and 5.5 V VP simultaneously?
Yes, the ADF4106BCPZ-RL explicitly supports AVDD/DVDD = 3.3 V and VP = 5.5 V simultaneously, as stated in the Absolute Maximum Ratings (Table 3) and Power Supplies section (Table 1). This configuration enables full 0–5 V VCO tuning range while maintaining 3.3 V logic compatibility, and is validated in typical performance plots (Figures 6, 14, 16) using VP = 5 V with VDD = 3 V.
ADF4106BCPZ-RL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF)
- PLL:
- Yes
- Input:
- CMOS, TTL
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:1
- Differential - Input:Output:
- Yes/No
- Frequency - Max:
- 6GHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 2.7V ~ 3.3V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-LFCSP (4x4)
ADF4106BCPZ-RL FAQ
1.How can I place an order for ADF4106BCPZ-RL through Aetrix?
Please submit a Request for Quotation (RFQ) for ADF4106BCPZ-RL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADF4106BCPZ-RL reliable?
The price and inventory of ADF4106BCPZ-RL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADF4106BCPZ-RL is usually 5 days.
3.What payment methods are accepted for ADF4106BCPZ-RL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADF4106BCPZ-RL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADF4106BCPZ-RL?
ADF4106BCPZ-RL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADF4106BCPZ-RL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADF4106BCPZ-RL?
For technical support, including ADF4106BCPZ-RL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADF4106BCPZ-RL requirements.
6.How does Aetrix verify that ADF4106BCPZ-RL is sourced from the original manufacturer or authorized distributors?
All ADF4106BCPZ-RL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADF4106BCPZ-RL meets industry standards.
7.What is the process for return or replacement of ADF4106BCPZ-RL?
All ADF4106BCPZ-RL units undergo pre-shipment inspection (PSI). If there is an issue with ADF4106BCPZ-RL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADF4106BCPZ-RL part is unused and in its original packaging.
Return procedure for ADF4106BCPZ-RL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADF4106BCPZ-RL Tags
-
CD74HCT4046AM96
Texas Instruments

-
MC14046BDWR2G
onsemi

-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments

-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.

-
CY2305SXI-1T
Infineon Technologies

-
570BILFT
Renesas

-
CDCE913PWR
Texas Instruments

-
CY2305SXI-1HT
Infineon Technologies

-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

