Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Analog Devices Inc. ADF4106BRU

Name: ADF4106BRU
Brand: Analog Devices Inc.
SKU: ADF4106BRU
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: ADF4106BRU

Manufacturer:: Analog Devices Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 16-TSSOP (0.173", 4.40mm Width)

Datasheet:: ADF4106BRU.pdf

Description:: IC CLK/FREQ SYNTH 16TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,151

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

ADF4106BRU from Analog Devices is a 6 GHz PLL frequency synthesizer IC used as a local oscillator in wireless transceivers' up/down-conversion stages. It integrates a phase-frequency detector, programmable dual-modulus prescaler (8/9, 16/17, 32/33, 64/65), 14-bit R counter, 13-bit B counter, and 6-bit A counter - enabling N = BP + A division with ≤104 MHz PFD frequency and −223 dBc/Hz normalized phase noise floor.

For engineers reviewing the ADF4106BRU datasheet, ADF4106BRU pinout, ADF4106BRU application, or ADF4106BRU equivalent, key selection criteria include its 2.7–3.3 V dual-supply operation, separate VP rail for extended tuning voltage (up to 5.5 V), 3-wire serial interface, analog/digital lock detect, and hardware/software power-down modes in RF synthesis designs.

Technical Context

The ADF4106BRU implements a fully integrated digital PLL core with CML-based RF input stage (RFINA/RFINB) feeding a synchronous 4/5-core dual-modulus prescaler. Its PFD operates up to 104 MHz and supports programmable antibacklash pulse width via ABP1/ABP2 bits to eliminate dead zone and suppress reference spurs.

Division architecture uses cascaded 14-bit R counter (REFIN divider), 13-bit B counter, and 6-bit A counter to realize N = BP + A feedback ratio, where P is selected from 8/9, 16/17, 32/33, or 64/65 - enabling fine frequency resolution while maintaining contiguous output coverage down to 500 MHz input.

Key Specifications

Parameter	Value and Actual Design Meaning
RF Input Range	0.5–6.0 GHz: supports direct RF injection without external frequency dividers in LMDS, satellite, and broadband wireless front-ends.
PFD Max Frequency	104 MHz: enables high reference frequencies and narrow loop bandwidths for low jitter in high-speed communication systems.
Normalized Phase Noise Floor	−223 dBc/Hz: defines fundamental PLL noise limit; critical for EVM-sensitive 5G and WiMAX base station LO design.
Charge Pump Current Range	625 µA–5 mA (programmable): allows optimization of loop filter dynamics and VCO tuning sensitivity across wide frequency bands.
Supply Voltages	AVDD/DVDD = 2.7–3.3 V; VP = AVDD to 5.5 V: decouples logic/analog rails and extends VCO tuning range beyond 3 V supply constraints.
Lock Detect Options	Analog (open-drain) and digital (CMOS) outputs: provide flexible system-level synchronization and fault monitoring in real-time RF control loops.
Serial Interface	3-wire (CLK/DATA/LE): enables compact microcontroller interfacing with deterministic 24-bit register loading and latch-select control.

Pinout & Package

ADF4106BRU is packaged in a 16-lead TSSOP (RoHS-compliant, JEDEC MO-153). Pin functions are validated per Analog Devices Rev. F datasheet Figure 3 and Table 4.

Pin/Terminal	Circuit Role	Design Meaning
RSET	Charge pump current calibration	Connects to CPGND via 5.1 kΩ resistor to set ICP = 5 mA; tolerance directly impacts loop gain accuracy and settling time.
CP	Charge pump output	Drives external loop filter; requires low-impedance path to VCO tuning port; sensitive to PCB parasitics affecting phase margin.
RFINA / RFINB	Differential RF input	Accepts ac-coupled 50 Ω RF signal up to 6 GHz; RFINB must be bypassed to AGND with 100 pF capacitor per layout guidelines.
REFIN	Reference clock input	CMOS-compatible (VDD/2 threshold); accepts 20–300 MHz crystal or oscillator signal; dc-biased internally at AVDD/2.
CLK / DATA / LE	3-wire serial interface	Supports MSB-first 24-bit register writes; LE edge triggers latch selection (R/N/Function/Init) based on DB1/DB0 control bits.
MUXOUT	Multiplexed diagnostic output	Configurable via M3/M2/M1 to output lock detect, scaled RF, or scaled REFIN - essential for in-system debug and calibration.
VP	Charge pump power supply	Independent rail (≥AVDD, ≤5.5 V) enables >3 V tuning voltage generation even with 3 V system supply - critical for wide-tuning VCOs.

Key Features

Feature	Design Value
Programmable dual-modulus prescaler	Four selectable P/P+1 ratios (8/9, 16/17, 32/33, 64/65) enable optimal N-divider configuration for contiguous frequency coverage and minimal fractional spurs.
Separate VP supply rail	Allows charge pump output swing up to 5.5 V while maintaining 3 V logic/analog supplies - eliminates need for external level-shifting in high-Vtune VCO applications.
Antibacklash pulse width control	Two-bit programmable ABP setting (via R counter latch) eliminates PFD dead zone and reduces reference spurs by >5 dB in typical 200 kHz PFD configurations.
Dual lock detect outputs	Simultaneous analog (open-drain) and digital (CMOS) lock signals support both fast microcontroller polling and robust hardware interlock in safety-critical RF subsystems.
Hardware/software power-down	CE pin assertion or F2 bit setting reduces total current to 10 µA - preserves system power budget during idle or sleep modes without losing register state.

Applications

Wireless Base Station Transmitter	Satellite Communication Uplink
Use Scenario: Generating stable 5.8 GHz LO for LTE/WiMAX base station power amplifier driver stage with <1° RMS integrated phase noise. IC Role / Device Role / Timing Role: Core PLL synthesizer providing frequency-agile, low-spur LO signal synchronized to 10 MHz network reference clock. Use Value: Enables 200 kHz PFD operation with 64/65 prescaler to achieve 100 kHz channel spacing and −76.5 dBc/Hz @1 kHz offset at 5.8 GHz - meeting 3GPP spectral mask requirements.	Use Scenario: Local oscillator in L-band upconverter for geostationary satellite telemetry transmitters requiring −92.5 dBc/Hz phase noise at 900 MHz. IC Role / Device Role / Timing Role: High-stability frequency synthesis element referenced to oven-controlled crystal oscillator (OCXO) with digital lock detect for telemetry health monitoring. Use Value: Achieves −92.5 dBc/Hz @1 kHz offset using 200 kHz PFD and 16/17 prescaler - satisfying CCSDS spectral purity mandates for deep-space link budgets.
Broadband Wireless Access (LMDS)	Test & Measurement Instrumentation
Use Scenario: 26 GHz millimeter-wave LO generation in LMDS subscriber unit using frequency multiplication chain anchored by ADF4106BRU at 6 GHz. IC Role / Device Role / Timing Role: First-stage synthesizer delivering ultra-low-noise 6 GHz reference to active multiplier, reducing doubler-induced phase noise degradation. Use Value: 6 GHz RF input capability and −223 dBc/Hz normalized phase noise floor minimize multiplied spurs - enabling >40 dB ACLR in 256-QAM LMDS modems.	Use Scenario: Agile LO source in vector signal analyzer front-end requiring rapid frequency hopping (<100 µs settling) and repeatable spectral purity across 500 MHz–6 GHz range. IC Role / Device Role / Timing Role: Programmable frequency generator controlled via SPI from FPGA host; MUXOUT used for real-time lock verification during sweep sequences. Use Value: Hardware power-down mode and 3-wire interface allow deterministic reconfiguration without bus contention - supporting <50 µs frequency switching in automated test equipment.

Wireless Base Station Transmitter

Satellite Communication Uplink

Use Scenario: Generating stable 5.8 GHz LO for LTE/WiMAX base station power amplifier driver stage with <1° RMS integrated phase noise.

IC Role / Device Role / Timing Role: Core PLL synthesizer providing frequency-agile, low-spur LO signal synchronized to 10 MHz network reference clock.

Use Value: Enables 200 kHz PFD operation with 64/65 prescaler to achieve 100 kHz channel spacing and −76.5 dBc/Hz @1 kHz offset at 5.8 GHz - meeting 3GPP spectral mask requirements.

Use Scenario: Local oscillator in L-band upconverter for geostationary satellite telemetry transmitters requiring −92.5 dBc/Hz phase noise at 900 MHz.

IC Role / Device Role / Timing Role: High-stability frequency synthesis element referenced to oven-controlled crystal oscillator (OCXO) with digital lock detect for telemetry health monitoring.

Use Value: Achieves −92.5 dBc/Hz @1 kHz offset using 200 kHz PFD and 16/17 prescaler - satisfying CCSDS spectral purity mandates for deep-space link budgets.

Broadband Wireless Access (LMDS)

Test & Measurement Instrumentation

Use Scenario: 26 GHz millimeter-wave LO generation in LMDS subscriber unit using frequency multiplication chain anchored by ADF4106BRU at 6 GHz.

IC Role / Device Role / Timing Role: First-stage synthesizer delivering ultra-low-noise 6 GHz reference to active multiplier, reducing doubler-induced phase noise degradation.

Use Value: 6 GHz RF input capability and −223 dBc/Hz normalized phase noise floor minimize multiplied spurs - enabling >40 dB ACLR in 256-QAM LMDS modems.

Use Scenario: Agile LO source in vector signal analyzer front-end requiring rapid frequency hopping (<100 µs settling) and repeatable spectral purity across 500 MHz–6 GHz range.

IC Role / Device Role / Timing Role: Programmable frequency generator controlled via SPI from FPGA host; MUXOUT used for real-time lock verification during sweep sequences.

Use Value: Hardware power-down mode and 3-wire interface allow deterministic reconfiguration without bus contention - supporting <50 µs frequency switching in automated test equipment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PLL synthesizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADF4153AACPZ-R7	Integrated VCO (4.4–5.6 GHz); no external VCO required; lower max RF input (5.6 GHz); 32-lead LFCSP only.	Eliminates external loop filter/VCO but sacrifices frequency flexibility and tuning range scalability.	Select when board space and BOM count reduction outweigh need for multi-band VCO support or >5.6 GHz operation.
HMC703LP4E	Higher PFD max frequency (135 MHz); wider charge pump range (0.3–10 mA); 24-lead QFN; no separate VP rail.	Lacks VP rail for extended tuning voltage - limits compatibility with high-Vtune VCOs requiring >3.3 V tuning range.	Select for ultra-fast lock time and higher PFD frequencies in fixed-band instrumentation, where VP independence is not required.

Compared with ADF4106BRU, ADF4153AACPZ-R7 integrates the VCO to reduce component count but constrains frequency agility, while HMC703LP4E offers faster PFD rates and broader ICP range yet omits the VP rail - making ADF4106BRU uniquely suited for wide-tuning, multi-band RF systems needing independent charge pump headroom.

Availability

ADF4106BRU is available at Aetrix Electronics and suitable for broadband wireless access infrastructure, satellite communication terminals, and RF test instrumentation requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for ADF4106BRU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and RF ICs, serving precision instrumentation, communications, and industrial markets since 1965.

The ADF4106BRU belongs to Analog Devices' PLL frequency synthesizer product line, designed specifically for high-frequency, low-phase-noise local oscillator generation in wireless infrastructure and aerospace applications.

FAQ

What is the maximum RF input frequency supported by the ADF4106BRU?

The ADF4106BRU supports an RF input frequency range of 0.5 GHz to 6.0 GHz, as specified in the Rev. F datasheet Table 1. This 6 GHz bandwidth enables direct synthesis for LMDS, satellite uplinks, and WiMAX base stations without requiring pre-scaling. Operation below 0.5 GHz requires slew rate >320 V/µs to ensure proper prescaler triggering.

How does the separate VP supply rail benefit ADF4106BRU system design?

The VP rail on the ADF4106BRU allows the charge pump to operate up to 5.5 V independently of the 2.7–3.3 V AVDD/DVDD supplies. This enables direct drive of wide-tuning VCOs requiring >3.3 V control voltage - eliminating level-shifters or charge pumps. In a 3 V system, setting VP = 5 V extends usable VCO tuning range by ~2 V, improving frequency coverage and loop stability.

Which prescaler ratios are programmable on the ADF4106BRU?

The ADF4106BRU supports four programmable dual-modulus prescaler ratios: 8/9, 16/17, 32/33, and 64/65. These are selected via the P1/P2 bits in the Function Latch (Table 6, DB17/DB16). The choice affects minimum N-divider value (P²−P) and contiguous frequency coverage - e.g., P=64 enables finer resolution at high RF frequencies but requires lower PFD rates.

Does the ADF4106BRU include lock detection functionality?

Yes, the ADF4106BRU provides both analog and digital lock detect outputs via the MUXOUT pin. Digital lock detect is CMOS-compatible and asserts high after three (LDP=0) or five (LDP=1) consecutive PFD cycles with phase error <15 ns. Analog lock detect is open-drain and pulses low upon loss of lock - both are configurable without external components and support real-time system monitoring.

What package type is used for the ADF4106BRU variant?

The ADF4106BRU is supplied in a 16-lead TSSOP package (JEDEC MO-153, 5 mm × 4.4 mm × 1.2 mm), as confirmed in the Rev. F datasheet Figure 3 and Ordering Guide. This RoHS-compliant package features exposed paddle thermal enhancement and is distinct from the 20-lead LFCSP variant (ADF4106BCPZ).

ADF4106BRU Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 16-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Clock/Frequency Synthesizer (RF)

PLL:: Yes

Input:: CMOS, TTL

Output:: Clock

Number of Circuits:: 1

Ratio - Input:Output:: 2:1

Differential - Input:Output:: Yes/No

Frequency - Max:: 6GHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 2.7V ~ 3.3V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 16-TSSOP

ADF4106BRU FAQ

1.How can I place an order for ADF4106BRU through Aetrix?

Please submit a Request for Quotation (RFQ) for ADF4106BRU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADF4106BRU reliable?

The price and inventory of ADF4106BRU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADF4106BRU is usually 5 days.

3.What payment methods are accepted for ADF4106BRU?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADF4106BRU transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADF4106BRU?

ADF4106BRU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADF4106BRU order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADF4106BRU?

For technical support, including ADF4106BRU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADF4106BRU requirements.

6.How does Aetrix verify that ADF4106BRU is sourced from the original manufacturer or authorized distributors?

All ADF4106BRU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADF4106BRU meets industry standards.

7.What is the process for return or replacement of ADF4106BRU?

All ADF4106BRU units undergo pre-shipment inspection (PSI). If there is an issue with ADF4106BRU, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADF4106BRU part is unused and in its original packaging.

Return procedure for ADF4106BRU:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…