Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Analog Devices Inc. ADF4106SRUZ-EP-R7

Name: ADF4106SRUZ-EP-R7
Brand: Analog Devices Inc.
SKU: ADF4106SRUZ-EP-R7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: ADF4106SRUZ-EP-R7

Manufacturer:: Analog Devices Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 16-TSSOP (0.173", 4.40mm Width)

Datasheet:: ADF4106SRUZ-EP-R7.pdf

Description:: IC PLL FREQ SYNTHESIZER 16TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,359

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

ADF4106SRUZ-EP-R7 from Analog Devices is a radiation-hardened, military-grade PLL frequency synthesizer IC designed for local oscillator generation in up-conversion and down-conversion stages of RF systems. It supports RF input frequencies up to 6.0 GHz, operates across −55°C to +125°C, features dual-modulus prescalers (8/9, 16/17, 32/33, 64/65), programmable charge pump currents (625 µA to 5 mA), and integrates analog/digital lock detect. It is used in satellite transceivers requiring stable phase-locked reference synthesis under extreme thermal and radiation conditions.

For engineers reviewing the ADF4106SRUZ-EP-R7 datasheet, ADF4106SRUZ-EP-R7 pinout, ADF4106SRUZ-EP-R7 application, or ADF4106SRUZ-EP-R7 equivalent, key selection considerations include its 6 GHz RF bandwidth, extended tuning voltage capability via separate VP supply, 3-wire serial interface timing compliance (t1 ≥10 ns setup), −55°C to +125°C operation, and qualification for defense/aerospace use per AQEC standards.

Technical Context

The ADF4106SRUZ-EP-R7 implements a digital phase-frequency detector (PFD) with antibacklash pulse control, a precision charge pump with RSET-programmable current, and a fully programmable N-divider formed by 6-bit A and 13-bit B counters plus dual-modulus prescaler (P/P+1). Its architecture enables N = BP + A division with 14-bit R counter for flexible REFIN scaling.

It supports two distinct power domains: AVDD/DVDD (2.7 V–3.3 V) for logic and analog core, and VP (AVDD to 5.5 V) for extended charge pump output swing-critical for driving wide-tuning-range VCOs. Lock detection is provided both analog (via MUXOUT) and digital (dedicated LOCK pin), and hardware/software power-down modes reduce quiescent current to 10 µA.

Key Specifications

Parameter	Value and Actual Design Meaning
RF Input Frequency	0.5 GHz to 6.0 GHz - supports direct RF synthesis up to X-band without frequency doublers.
Operating Temperature	−55°C to +125°C - qualified for military and space-grade embedded systems with no derating.
Charge Pump Current	625 µA to 5 mA (programmable via RSET) - enables precise loop filter design across wide bandwidths (e.g., 20 kHz to 100 kHz).
PFD Frequency Max	104 MHz - allows high-resolution frequency steps and fast lock times in narrowband applications.
Phase Noise Floor	−223 dBc/Hz - low normalized noise floor ensures minimal in-band jitter contribution to VCO output.
Reference Spurs	−65 dBc to −92 dBc - measured spurious levels enable clean LO generation in sensitive receiver front-ends.
Supply Voltages	AVDD/DVDD = 2.7–3.3 V; VP = AVDD to 5.5 V - independent VP rail extends VCO tuning voltage range beyond 3 V systems.

Pinout & Package

ADF4106SRUZ-EP-R7 is packaged in a 16-lead TSSOP (RU-16) with exposed pad not present - distinct from the LFCSP variant. Pin functions are electrically identical to the ADF4106-EP family but mapped to RU-16 mechanical outline per JEDEC MO-153-AB.

Pin	Circuit Role	Design Meaning
1	RSET	Resistor connection point setting max charge pump current (ICP = 5.25 kΩ / RSET); nominal voltage 0.66 V.
2	CP	Charge pump output node - delivers ±ICP current to external loop filter; requires low-impedance path to VCO tuning line.
3	CPGND	Dedicated ground return for charge pump - must be star-connected to minimize noise coupling into CP node.
4	AGND	Analog ground for prescaler and PFD - isolated from DGND to suppress digital switching noise on RF path.
5	RFINB	Complementary RF input to prescaler - differential pair with RFINA; requires 100 pF AC coupling to ground.
6	RFINA	Primary RF input to prescaler - accepts ac-coupled VCO output up to 6 GHz; slew rate >320 V/µs required below 0.5 GHz.
7	AVDD	Analog power supply (2.7–3.3 V) - must be decoupled with 100 nF + 10 nF capacitors close to pin.
8	REFIN	CMOS reference input (20–300 MHz) - biased at AVDD/2; accepts TTL/CMOS oscillators or ac-coupled crystal sources.
9	CE	Active-low chip enable - asserts hardware power-down mode; reduces IDD to 10 µA when low.
10	DGND	Digital ground return - separates logic noise from analog sections; connected to AGND only at single point.
11	CLK	Serial clock input - latches DATA on rising edge; min 10 ns setup/hold required per timing spec.
12	DATA	24-bit serial data input (MSB first) - includes 2 LSB control bits selecting latch destination (R/A/B/Function).
13	LE	Load enable - transfers shift register contents to selected internal latch on rising edge.
14	MUXOUT	Configurable output - selectable between lock detect signal, scaled RF, or scaled REFIN for debug or monitoring.
15	DVDD	Digital power supply (2.7–3.3 V) - matched to AVDD; decoupling required adjacent to pin.
16	VP	Charge pump power supply (≥AVDD, ≤5.5 V) - enables 0–5 V tuning voltage range in 3 V systems.

Key Features

Feature	Design Value
Separate VP supply rail	Enables 5 V tuning voltage headroom in 3 V systems - eliminates need for external charge pump boosters in wide-VCO designs.
Programmable antibacklash pulse	Adjustable width prevents false PFD locking during frequency sweeps - critical for agile synthesizer applications.
Dual-modulus prescaler options	8/9, 16/17, 32/33, 64/65 - provides optimal resolution vs. speed trade-off across 0.5–6 GHz RF band.
Analog + digital lock detect	Redundant lock verification - analog MUXOUT output and digital LOCK pin improve system reliability in safety-critical links.
Controlled manufacturing baseline	Single fab site, single assembly/test site, and product change notification - ensures long-term supply continuity for defense programs.

Applications

Satellite Uplink Transmitter	Defense Radar Local Oscillator
Use Scenario: Generating stable 5.8 GHz LO for QPSK uplink modulation in LEO satellite payloads operating across −55°C to +125°C. IC Role / Device Role / Timing Role: PLL frequency synthesizer providing phase-locked reference to mixer; N-divider configured for integer-N synthesis with 200 kHz PFD frequency. Use Value: −76.5 dBc/Hz phase noise at 1 kHz offset enables <1° RMS jitter in demodulated symbol timing - meeting CCSDS spectral purity requirements.	Use Scenario: Agile LO source in X-band pulse-Doppler radar front-end requiring rapid frequency hopping and deterministic lock time. IC Role / Device Role / Timing Role: Core PLL synthesizer driving VCO with 0–5 V tuning range; CE pin used for synchronized power cycling between chirps. Use Value: Hardware power-down mode reduces standby current to 10 µA - extending battery life in portable radar units without compromising wake-up latency.
Secure Military Radio Transceiver	Test Equipment Local Oscillator
Use Scenario: Frequency-agile LO in SDR-based tactical radio supporting multi-band waveforms (e.g., SINCGARS, HAVE QUICK II) in harsh environments. IC Role / Device Role / Timing Role: Programmable synthesizer implementing channelized LO generation; 3-wire interface controlled by FPGA for real-time reconfiguration. Use Value: Dual-modulus prescaler (32/33) enables 100 kHz channel spacing at 2.4 GHz while maintaining <20 µs lock time - satisfying MIL-STD-188-181B agility requirements.	Use Scenario: Reference source in broadband spectrum analyzer requiring ultra-low spurious content and calibrated phase noise performance. IC Role / Device Role / Timing Role: Precision LO generator locked to 10 MHz OCXO; MUXOUT used to monitor lock status and scaled REFIN for internal calibration. Use Value: −90 dBc reference spurs at 200 kHz offset ensure measurement accuracy to −120 dBm - meeting IEEE 1057 dynamic range specifications.

Satellite Uplink Transmitter

Defense Radar Local Oscillator

Use Scenario: Generating stable 5.8 GHz LO for QPSK uplink modulation in LEO satellite payloads operating across −55°C to +125°C.

IC Role / Device Role / Timing Role: PLL frequency synthesizer providing phase-locked reference to mixer; N-divider configured for integer-N synthesis with 200 kHz PFD frequency.

Use Value: −76.5 dBc/Hz phase noise at 1 kHz offset enables <1° RMS jitter in demodulated symbol timing - meeting CCSDS spectral purity requirements.

Use Scenario: Agile LO source in X-band pulse-Doppler radar front-end requiring rapid frequency hopping and deterministic lock time.

IC Role / Device Role / Timing Role: Core PLL synthesizer driving VCO with 0–5 V tuning range; CE pin used for synchronized power cycling between chirps.

Use Value: Hardware power-down mode reduces standby current to 10 µA - extending battery life in portable radar units without compromising wake-up latency.

Secure Military Radio Transceiver

Test Equipment Local Oscillator

Use Scenario: Frequency-agile LO in SDR-based tactical radio supporting multi-band waveforms (e.g., SINCGARS, HAVE QUICK II) in harsh environments.

IC Role / Device Role / Timing Role: Programmable synthesizer implementing channelized LO generation; 3-wire interface controlled by FPGA for real-time reconfiguration.

Use Value: Dual-modulus prescaler (32/33) enables 100 kHz channel spacing at 2.4 GHz while maintaining <20 µs lock time - satisfying MIL-STD-188-181B agility requirements.

Use Scenario: Reference source in broadband spectrum analyzer requiring ultra-low spurious content and calibrated phase noise performance.

IC Role / Device Role / Timing Role: Precision LO generator locked to 10 MHz OCXO; MUXOUT used to monitor lock status and scaled REFIN for internal calibration.

Use Value: −90 dBc reference spurs at 200 kHz offset ensure measurement accuracy to −120 dBm - meeting IEEE 1057 dynamic range specifications.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PLL frequency synthesizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADF4153AACPZ-R7	Higher max PFD frequency (200 MHz), integrated LDO, but lower RF input max (4.4 GHz); RoHS-compliant LFCSP only.	Optimized for commercial test equipment; lacks AQEC qualification and −55°C rating.	Select for cost-sensitive, non-military 4 GHz systems where integrated regulation simplifies power design.
HMC703LP4E	Wider RF range (up to 13 GHz), fractional-N architecture, higher phase noise floor (−219 dBc/Hz); requires external VCO and loop filter.	Targets millimeter-wave 5G and EW systems; not qualified for extended temperature or defense use.	Select when >6 GHz operation or sub-Hz frequency resolution is required, accepting higher complexity and no military qualification.

Compared with ADF4106SRUZ-EP-R7, ADF4153AACPZ-R7 trades military reliability for integration and cost, while HMC703LP4E sacrifices environmental ruggedness and simplicity for extended frequency coverage and fractional-N flexibility - making ADF4106SRUZ-EP-R7 the sole choice for radiation-tolerant, wide-temperature, integer-N LO generation in defense platforms.

Availability

ADF4106SRUZ-EP-R7 is available at Aetrix Electronics and suitable for satellite communications, defense radar, secure military radios, and aerospace instrumentation requiring stable component supply across extended temperature and long lifecycle commitments.

Supply support for ADF4106SRUZ-EP-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and defense markets since 1965.

The ADF4106-EP product line delivers radiation-tolerant, temperature-extended PLL synthesizers for mission-critical RF subsystems in space, airborne, and ground-based defense platforms - emphasizing reliability, controlled manufacturing, and AQEC compliance over consumer-grade metrics.

FAQ

What is the maximum RF input frequency supported by the ADF4106SRUZ-EP-R7?

The ADF4106SRUZ-EP-R7 supports an RF input frequency range of 0.5 GHz to 6.0 GHz. This upper limit is validated per Table 1 in the Rev. D datasheet under "RF Input Frequency (RFIN)" with test condition "max" and applies directly to the ADF4106SRUZ-EP-R7 variant in its 16-lead TSSOP package. Operation above 6 GHz is not specified or guaranteed.

Does the ADF4106SRUZ-EP-R7 require an external loop filter?

Yes, the ADF4106SRUZ-EP-R7 requires an external passive loop filter between its CP pin and the VCO tuning input. The IC contains only the PFD, charge pump, and dividers - it does not integrate filter components. Design of the loop filter determines PLL bandwidth, stability, and transient response; Analog Devices' ADIsimPLL tool is recommended for sizing.

What is the purpose of the VP pin on the ADF4106SRUZ-EP-R7?

The VP pin on the ADF4106SRUZ-EP-R7 supplies the charge pump independently from AVDD/DVDD, allowing VP to be set up to 5.5 V even when AVDD = 3.3 V. This extends the tuning voltage range delivered to the VCO - enabling full utilization of wide-tuning-range VCOs (e.g., 0–5 V) without external level-shifting circuitry.

Is the ADF4106SRUZ-EP-R7 pin-compatible with the standard ADF4106BRUZ?

No, the ADF4106SRUZ-EP-R7 is not pin-compatible with the commercial ADF4106BRUZ. While both use 16-lead TSSOP packages, the ADF4106SRUZ-EP-R7 is an enhanced product with different internal biasing, extended temperature qualification, and AQEC-specific test flow. Pin functions match the ADF4106-EP family, but electrical behavior and reliability specs differ significantly.

How is lock detection implemented on the ADF4106SRUZ-EP-R7?

The ADF4106SRUZ-EP-R7 provides dual lock detection: analog lock status is available on the MUXOUT pin (configurable via register bit), and a dedicated digital LOCK pin outputs a CMOS-level signal. Both signals indicate stable phase lock after programmable lock-detect window timing - enabling redundant verification in safety-critical RF chains.

ADF4106SRUZ-EP-R7 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 16-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 16-TSSOP

ADF4106SRUZ-EP-R7 FAQ

1.How can I place an order for ADF4106SRUZ-EP-R7 through Aetrix?

Please submit a Request for Quotation (RFQ) for ADF4106SRUZ-EP-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADF4106SRUZ-EP-R7 reliable?

The price and inventory of ADF4106SRUZ-EP-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADF4106SRUZ-EP-R7 is usually 5 days.

3.What payment methods are accepted for ADF4106SRUZ-EP-R7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADF4106SRUZ-EP-R7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADF4106SRUZ-EP-R7?

ADF4106SRUZ-EP-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADF4106SRUZ-EP-R7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADF4106SRUZ-EP-R7?

For technical support, including ADF4106SRUZ-EP-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADF4106SRUZ-EP-R7 requirements.

6.How does Aetrix verify that ADF4106SRUZ-EP-R7 is sourced from the original manufacturer or authorized distributors?

All ADF4106SRUZ-EP-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADF4106SRUZ-EP-R7 meets industry standards.

7.What is the process for return or replacement of ADF4106SRUZ-EP-R7?

All ADF4106SRUZ-EP-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADF4106SRUZ-EP-R7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADF4106SRUZ-EP-R7 part is unused and in its original packaging.

Return procedure for ADF4106SRUZ-EP-R7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…