Analog Devices Inc. ADF4112BRU

Overview

ADF4112BRU from Analog Devices is a 3.0 GHz RF PLL frequency synthesizer IC used as a local oscillator in wireless transceiver upconversion/downconversion stages. It features a dual-modulus prescaler (8/9, 16/17, 32/33, 64/65), programmable charge pump current (625 µA to 5 mA), 3-wire serial interface, and operates from 2.7 V to 5.5 V supply with separate VP pin for extended tuning voltage. It supports GSM, WCDMA, and wireless LAN base station applications.

For engineers reviewing the ADF4112BRU datasheet, ADF4112BRU pinout, ADF4112BRU application, or ADF4112BRU equivalent, key selection criteria include its 0.2–3.0 GHz RF input range (3 V operation), 200 kHz maximum PFD frequency, −90 dBc/Hz phase noise at 900 MHz/1 kHz offset, lock detect capability, and TSSOP-16 package compatibility with industrial temperature range (−40°C to +85°C).

Technical Context

The ADF4112BRU implements a digital phase-frequency detector (PFD) and precision charge pump driving an external loop filter and VCO. Its N-divider architecture uses 13-bit B and 6-bit A counters with dual-modulus prescaler (P/P+1) to achieve integer-N synthesis, where N = BP + A. The 14-bit R counter enables flexible reference input division.

It supports analog and digital lock detection, hardware/software power-down modes, and programmable antibacklash pulse width to suppress reference spurs. The separate VP supply (AVDD ≤ VP ≤ 6.0 V) allows 6 V tuning voltage generation in 3 V systems, critical for wide-range VCO control in RF front-ends.

Key Specifications

Pinout & Package

ADF4112BRU is housed in a 16-lead TSSOP package (RoHS-compliant, JEDEC MO-153). The exposed paddle is not present - unlike LFCSP variants - and no thermal pad connection is required.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar RF PLL synthesizer applications.

Compared with ADF4112BRU, the ADF4153A offers higher frequency and lower noise but removes analog lock detect and VP flexibility, while the LMX2531LQ1730E integrates a VCO at the cost of higher power and incompatible control logic - making ADF4112BRU optimal for discrete VCO-based industrial wireless infrastructure where tuning range and proven reliability are prioritized.

Availability

ADF4112BRU is available at Aetrix Electronics and suitable for wireless base stations, handheld transceivers, and communications test equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for ADF4112BRU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and RF ICs, headquartered in Norwood, MA, serving industrial, automotive, communications, and healthcare markets.

The ADF411x family was designed specifically for cost-sensitive, high-volume wireless infrastructure and handset applications requiring robust integer-N PLL performance with flexible power and interface options - emphasizing manufacturability, thermal stability, and interoperability with discrete VCOs.

FAQ

What is the maximum RF input frequency supported by the ADF4112BRU at 3 V supply?

The ADF4112BRU supports an RF input frequency range of 0.2 GHz to 3.0 GHz when operating at 3 V supply (AVDD = DVDD = 3 V). This is explicitly specified in Table 1 under "RF Input Frequency" for ADF4112 with "Input level = −10 dBm" condition. Operation below 0.2 GHz requires slew rate >75 V/µs to ensure proper prescaler triggering.

Does the ADF4112BRU require an external loop filter, and why?

Yes, the ADF4112BRU requires an external passive loop filter between its CP pin and the VCO tuning input. The IC contains only the PFD, charge pump, and dividers - it does not integrate a loop filter or VCO. The filter shapes the PLL transfer function to achieve desired phase margin, lock time, and reference spur suppression, and its component values depend directly on the selected ICP and VCO gain (Kvco).

How does the VP pin improve VCO tuning range in the ADF4112BRU?

The VP pin allows the charge pump output voltage swing to extend up to 6.0 V independently of the 2.7–5.5 V AVDD/DVDD rails. When AVDD = 3 V but VP = 6 V, the CP can drive the loop filter to produce up to ~5.5 V tuning voltage - effectively doubling the usable range compared to tying VP to AVDD. This enables direct interfacing with high-tuning-range VCOs common in broadband wireless infrastructure.

Can the ADF4112BRU generate fractional-N frequencies, or is it integer-N only?

The ADF4112BRU is strictly an integer-N PLL synthesizer. It implements only A/B counters and a dual-modulus prescaler (P/P+1) to realize N = BP + A, with no sigma-delta modulator or fractional divider. Fractional-N capability requires devices like the ADF4153 or ADF4350. Attempting fractional division with ADF4112BRU results in spurious outputs and loss of lock.

What is the purpose of the RSET pin, and how is it configured for 5 mA charge pump current?

The RSET pin sets the maximum charge pump current (ICPmax) via an external resistor to CPGND. The relationship is ICPmax = 5.23 / RSET(kΩ). To achieve 5 mA, a 4.7 kΩ resistor is used (5.23 / 4.7 ≈ 5.0 mA), as confirmed in Table 1 and Figure 27 of the datasheet. This value optimizes loop filter design for typical VCO gains while maintaining charge pump linearity.