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Analog Devices Inc. ADF4113BCP

Part No.:
ADF4113BCP
Manufacturer:
Analog Devices Inc.
Category:
Clock Generators, PLLs, Frequency Synthesizers
Package:
20-WFQFN Exposed Pad, CSP
Datasheet:
AetrixADF4113BCP.pdf
Description:
IC PLL FREQ SYNTHESIZER 20-LFCSP
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:1,935

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Product details

Overview

ADF4113BCP from Analog Devices is a 4.0 GHz RF PLL frequency synthesizer IC used as a local oscillator in up/downconversion stages of wireless transceivers. It features dual-modulus prescaler (8/9 to 64/65), programmable charge pump current (up to 5 mA), 3-wire serial interface, and operates from 2.7 V to 5.5 V supply. It enables precise frequency synthesis in GSM, WCDMA, and wireless LAN base stations.

For engineers reviewing the ADF4113BCP datasheet, ADF4113BCP pinout, ADF4113BCP application, or ADF4113BCP equivalent, key selection considerations include its 4.0 GHz RF input range, 200 MHz max prescaler output frequency at 5 V, −100 dBc reference spurs at 900 MHz, integrated phase-frequency detector with lock detect, and LFCSP-20 package compatibility with high-density RF layouts.

Technical Context

The ADF4113BCP implements a digital phase-frequency detector (PFD) and precision charge pump driving an external loop filter and VCO. Its N-divider uses 13-bit B and 6-bit A counters with dual-modulus prescaler (P/P+1), enabling integer-N synthesis where N = BP + A. The 14-bit R counter supports programmable reference input frequencies from 5 MHz to 104 MHz.

It supports both analog and digital lock detection, hardware/software power-down modes, and separate VP supply (up to 6.0 V) for extended tuning voltage in 3 V systems. Charge pump current is set via external RSET resistor (2.7 kΩ–10 kΩ), delivering ±625 µA to ±5 mA with 2% sink/source matching and 2.5% absolute accuracy.

Key Specifications

ParameterValue and Actual Design Meaning
RF Input Frequency0.2 GHz to 4.0 GHz (at −5 dBm input level); enables direct synthesis up to cellular/WLAN bands without prescaler division bottlenecks.
Max Prescaler Output Freq200 MHz (at 5 V supply); constrains minimum prescaler ratio selection for given RF input to avoid CMOS counter saturation.
Charge Pump CurrentProgrammable 625 µA to 5 mA (via RSET); sets loop filter gain and impacts lock time, phase noise, and spurious performance.
PFD Max Frequency55 MHz; defines maximum reference comparison rate, directly limiting achievable channel spacing and loop bandwidth.
Supply Voltage Range2.7 V to 5.5 V (AVDD/DVDD); supports single-supply operation across industrial voltage rails with VP ≥ AVDD up to 6.0 V.
Phase Noise Floor−215 dBc/Hz normalized; determines ultimate spectral purity limit independent of VCO contribution.
Reference Spurs−100 dBc / −110 dBc at 200 kHz/400 kHz offset (900 MHz output); critical for adjacent-channel interference in dense spectrum deployments.

Pinout & Package

ADF4113BCP is housed in a 20-lead LFCSP (Lead Frame Chip Scale Package) with exposed paddle, requiring soldering of the EPAD to AGND for thermal and electrical integrity. Package dimensions: 4 mm × 4 mm × 0.85 mm (body), 0.5 mm pitch.

Pin/TerminalCircuit RoleDesign Meaning
RSETCharge pump current settingResistor-to-ground sets ICPmax per ICP = 5.23/RSET (kΩ) mA; nominal 0.56 V bias enables stable current sourcing/sinking.
CPCharge pump outputDelivers bidirectional ±ICP current to external loop filter; requires low-impedance path to VCO tuning port.
CPGNDCharge pump ground returnDedicated low-noise ground path isolates CP current return from digital/analog grounds to minimize injection noise.
RFINA / RFINBDifferential RF inputAccepts ac-coupled VCO output; RFINB is complementary - both require 100 pF bypass to AGND for optimal high-frequency termination.
REFINReference clock inputCMOS input (threshold ≈ DVDD/2) accepting 5–104 MHz; supports TTL/CMOS oscillators or ac-coupled crystal sources.
DATA / CLK / LE3-wire serial interface24-bit shift register control: MSB-first loading with two LSBs as latch-select control bits; LE rising edge transfers data to active register.
CEChip enableActive-low global shutdown; places CP in 3-state and disables internal logic, reducing quiescent current to 1 µA.
MUXOUTMultiplexed diagnostic outputSelectably outputs lock detect signal, scaled RF (÷16), or scaled REFIN (÷R) for real-time PLL status monitoring.

Key Features

FeatureDesign Value
Dual-modulus prescalerConfigurable 8/9, 16/17, 32/33, or 64/65 ratios - enables wide RF coverage while maintaining PFD frequency within 55 MHz limit.
Separate VP supplyVP ≥ AVDD up to 6.0 V allows 3 V system designs to drive VCOs requiring >3 V tuning range without level-shifting circuitry.
Antibacklash pulse widthProgrammable to suppress false PFD pulses during phase transitions - reduces reference spurs and improves transient stability.
Lock detect circuitryDual analog/digital lock detection provides reliable PLL acquisition verification for safety-critical or automated calibration sequences.
Low-power sleep mode1 µA typical standby current enables rapid wake-up in battery-powered or duty-cycled RF systems without full reinitialization.

Applications

Wireless Base Station TransmitterCellular Handset Local Oscillator

Use Scenario: Generating stable LO signals for upconversion in macrocell BTS power amplifiers operating in 1.8–2.2 GHz DCS/WCDMA bands.

IC Role / Device Role / Timing Role: Integer-N PLL synthesizer providing phase-coherent LO with <200 µs lock time and −100 dBc reference spurs.

Use Value: Enables compliant ACLR performance without external spur suppression filters, reducing BOM count and board area.

Use Scenario: Providing agile LO for direct-conversion receivers in multi-band GSM/PCS/DCS handsets.

IC Role / Device Role / Timing Role: Low-noise frequency synthesizer supporting fast hopping (≤500 µs) and simultaneous dual-band operation.

Use Value: Achieves −91 dBc/Hz phase noise at 1 kHz offset (900 MHz), meeting stringent EVM requirements for EDGE modulation.

Wireless LAN (802.11a/n/ac) RadioCommunications Test Equipment LO

Use Scenario: Synthesizing 5.15–5.85 GHz U-NII band LOs in WLAN access point RF front-ends.

IC Role / Device Role / Timing Role: High-frequency PLL core supporting 20/40/80 MHz channel bandwidths with minimal fractional-N artifacts.

Use Value: Delivers 4.0 GHz RF input capability and −85 dBc/Hz phase noise at 1960 MHz, ensuring clean EVM across OFDM subcarriers.

Use Scenario: Serving as programmable LO source in vector signal analyzers and RF signal generators requiring wideband agility.

IC Role / Device Role / Timing Role: Precision frequency reference generator with programmable PFD frequency and deterministic lock behavior.

Use Value: Supports 1 MHz PFD operation at 3100 MHz output with −86 dBc/Hz phase noise, enabling high-resolution spectral analysis.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PLL synthesizer applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
ADF4153AACPZ-R7Higher max RF input (6.0 GHz), integrated LDO, SPI interface, lower phase noise floor (−220 dBc/Hz).Targets newer 5G FR1 and mmWave test equipment where wider bandwidth and lower noise are mandatory.Choose ADF4153A when upgrading from ADF4113BCP for >4 GHz coverage or integrated power management.
LMX2531LQ1525E/NOPB3.1 GHz max RF input, fractional-N architecture, integrated VCO, smaller 24-pin QFN package.Better suited for compact handhelds or cost-sensitive consumer radios where on-chip VCO eliminates external component count.Choose LMX2531 when board space is constrained and integrated VCO simplifies design, accepting 3.1 GHz ceiling.

Compared with ADF4113BCP, ADF4153A offers higher frequency headroom and improved noise but requires SPI redesign; LMX2531 trades off max frequency and discrete VCO flexibility for integration and footprint reduction - neither is pin-compatible, and all require loop filter re-optimization.

Availability

ADF4113BCP is available at Aetrix Electronics and suitable for wireless infrastructure, cellular handset RF front-ends, and communications test equipment requiring stable component supply with guaranteed long-term availability.

Supply support for ADF4113BCP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and RF ICs, headquartered in Norwood, MA, serving industrial, communications, automotive, and aerospace markets since 1965.

The ADF411x family was designed specifically for cost-effective, high-reliability integer-N PLL synthesis in wireless infrastructure and portable radio applications - emphasizing low power, flexible prescaling, and robust lock detection.

FAQ

What is the maximum RF input frequency supported by the ADF4113BCP?

The ADF4113BCP supports an RF input frequency range of 0.2 GHz to 4.0 GHz when driven at −5 dBm input level. At lower input levels (e.g., −10 dBm), the upper limit drops to 3.7 GHz. This 4.0 GHz rating enables direct synthesis for LTE Band 40 (2.3 GHz), Band 41 (2.5 GHz), and unlicensed 5 GHz WLAN bands without requiring external prescaling.

How does the separate VP supply pin improve system design with the ADF4113BCP?

The VP pin on the ADF4113BCP accepts a supply up to 6.0 V, independent of AVDD/DVDD (2.7–5.5 V). This allows 3 V systems to deliver up to 6 V tuning voltage to external VCOs - eliminating level-shifters or charge pumps in wide-tuning-range applications such as broadband synthesizers or multiband front-ends.

Can the ADF4113BCP generate fractional-N frequencies?

No, the ADF4113BCP is an integer-N PLL synthesizer only. It lacks a sigma-delta modulator or fractional divider; frequency resolution is limited to fREFIN/R, where R is the programmable 14-bit reference divider. For fractional-N capability, consider Analog Devices' ADF415x or ADF435x families instead of the ADF4113BCP.

What is the purpose of the MUXOUT pin on the ADF4113BCP?

The MUXOUT pin on the ADF4113BCP is a configurable diagnostic output that can be programmed to provide lock detect status, a divided-by-16 version of the RF input, or a divided-by-R version of the reference input. This enables real-time PLL health monitoring and simplifies debug without requiring additional probing or external dividers.

Does the ADF4113BCP require external passive components to operate?

Yes - the ADF4113BCP requires an external loop filter between CP and the VCO tuning port, a resistor (RSET) from RSET to CPGND to set charge pump current, and decoupling capacitors on AVDD, DVDD, and VP. It also needs ac-coupling capacitors on RFINA/RFINB and REFIN, plus proper RF grounding of the exposed paddle per Analog Devices' layout guidelines.

ADF4113BCP Specifications

Product attributes
Attribute value
Manufacturer:
Analog Devices Inc.
Series:
*
Package/Case:
20-WFQFN Exposed Pad, CSP
Packaging:
Bag
Product Status:
Obsolete
Programmable:
Not Verified
Type:
Clock/Frequency Synthesizer (RF)
PLL:
Yes
Input:
Clock
Output:
Clock
Number of Circuits:
-
Ratio - Input:Output:
2:1
Differential - Input:Output:
Yes/No
Frequency - Max:
4GHz
Divider/Multiplier:
Yes/No
Voltage - Supply:
2.7V ~ 5.5V
Operating Temperature:
-
Mounting Type:
Surface Mount
Grade:
-
Qualification:
-
Supplier Device Package:
20-LFCSP (4x4)

ADF4113BCP FAQ

1.How can I place an order for ADF4113BCP through Aetrix?

Please submit a Request for Quotation (RFQ) for ADF4113BCP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADF4113BCP reliable?

The price and inventory of ADF4113BCP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADF4113BCP is usually 5 days.

3.What payment methods are accepted for ADF4113BCP?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADF4113BCP transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADF4113BCP?

ADF4113BCP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADF4113BCP order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADF4113BCP?

For technical support, including ADF4113BCP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADF4113BCP requirements.

6.How does Aetrix verify that ADF4113BCP is sourced from the original manufacturer or authorized distributors?

All ADF4113BCP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADF4113BCP meets industry standards.

7.What is the process for return or replacement of ADF4113BCP?

All ADF4113BCP units undergo pre-shipment inspection (PSI). If there is an issue with ADF4113BCP, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADF4113BCP part is unused and in its original packaging.

Return procedure for ADF4113BCP:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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