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Analog Devices Inc. ADF4113BRU
- Part No.:
- ADF4113BRU
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ADF4113BRU.pdf
- Description:
- IC CLK/FREQ SYNTH 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,931
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Product details
Overview
ADF4113BRU from Analog Devices is a 4.0 GHz RF PLL frequency synthesizer IC used as a local oscillator in wireless transceiver up/downconversion stages. It features a dual-modulus prescaler (8/9, 16/17, 32/33, 64/65), programmable charge pump current up to 5 mA, 3-wire serial interface, and operates from 2.7 V to 5.5 V. It enables precise frequency synthesis in GSM, WCDMA, and wireless LAN base stations.
For engineers reviewing the ADF4113BRU datasheet, ADF4113BRU pinout, ADF4113BRU application, or ADF4113BRU equivalent, this page delivers verified electrical specifications, functional pin roles, real-world use cases in RF front-ends, and validated alternative parts for PLL design continuity and supply resilience.
Technical Context
The ADF4113BRU implements a digital phase-frequency detector (PFD) with analog charge pump, 14-bit R counter, 6-bit A counter, and 13-bit B counter driving a P/P+1 dual-modulus prescaler to realize N = BP + A division. Its architecture supports wideband tuning via external VCO and loop filter integration.
It provides both analog and digital lock detect outputs, hardware/software power-down modes, and separate VP supply (up to 6.0 V) enabling extended VCO tuning voltage range in 3 V systems - critical for high-frequency 4 GHz operation with low phase noise.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max RF Input Frequency | 4.0 GHz - supports full-band synthesis for WCDMA and LTE FDD/TDD bands up to Band 41. |
| Charge Pump Current | Programmable up to 5 mA - sets loop filter gain and impacts lock time & stability in closed-loop PLLs. |
| PFD Max Frequency | 55 MHz - enables high reference frequencies for reduced fractional spurs and faster settling. |
| Supply Voltage Range | 2.7 V to 5.5 V - compatible with industrial and battery-powered RF subsystems. |
| Phase Noise @ 900 MHz | −91 dBc/Hz @ 1 kHz offset - meets stringent spectral purity requirements for cellular base station LOs. |
| Spurious Output | −100 dBc typical @ 200 kHz offset - minimizes interference in adjacent channels during frequency hopping. |
| Operating Temp Range | −40°C to +85°C - qualified for industrial and outdoor wireless infrastructure deployment. |
Pinout & Package
ADF4113BRU is packaged in a 16-lead TSSOP (ROHS-compliant, JEDEC MO-153) with exposed paddle thermally connected to AGND. Pin 1 is RSET; pin 16 is VP. The package supports standard reflow profiles and offers thermal resistance θJA = 150.4°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RSET (Pin 1) | Charge pump current setting | Resistor to CPGND sets ICPmax; 4.7 kΩ yields 5 mA - directly tunes loop dynamics and lock speed. |
| CP (Pin 2) | Charge pump output | Drives external loop filter; bipolar ±ICP current source/sink - forms core of PLL feedback path. |
| CPGND (Pin 3) | Charge pump ground return | Dedicated low-noise ground for CP node - prevents coupling into sensitive analog VCO control line. |
| RFINA/RFINB (Pins 5–6) | Differential RF input | Accepts ac-coupled VCO signal; 0.2–4.0 GHz range - enables direct connection to wideband VCOs without buffer. |
| REFIN (Pin 8) | Reference clock input | CMOS-compatible 5–104 MHz input - accepts crystal oscillator or FPGA clock; internal 100 kΩ termination. |
| DATA/CLK/LE (Pins 12–13) | 3-wire serial interface | MSB-first 24-bit shift register control - allows dynamic reconfiguration of N, R, prescaler, and power modes. |
| CE (Pin 10) | Chip enable | Active-low hardware shutdown - reduces quiescent current to 1 µA; enables fast RF subsystem power gating. |
| MUXOUT (Pin 14) | Multiplexed diagnostic output | Selectable lock detect, scaled RF, or scaled REFIN - simplifies board-level validation without extra test points. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-modulus prescaler (8/9, 16/17, 32/33, 64/65) | Enables integer-N synthesis across 0.2–4.0 GHz while maintaining PFD frequency ≥10 kHz for stable loop operation. |
| Separate VP supply (AVDD ≤ VP ≤ 6.0 V) | Allows 6 V tuning voltage on 3 V system rails - extends VCO frequency range and improves phase noise at high frequencies. |
| Analog + digital lock detect | Provides redundant, low-latency PLL lock confirmation - essential for automatic frequency calibration in production test. |
| Programmable antibacklash pulse width | Reduces reference spurs by minimizing PFD dead zone effects - improves spectral purity without external compensation. |
| Hardware power-down mode | Reduces supply current to 1 µA - enables rapid RF section disable during sleep cycles in portable/wireless handsets. |
Applications
| GSM Base Station Transmitter | WCDMA Femtocell Local Oscillator |
|---|---|
|
Use Scenario: Generating 900 MHz and 1800 MHz LO signals for upconversion in macrocell BTS power amplifiers. IC Role / Device Role / Timing Role: Integer-N PLL synthesizer providing stable, low-phase-noise LO with fast lock time (<400 µs). Use Value: −91 dBc/Hz phase noise at 1 kHz offset ensures ACLR compliance; 4.0 GHz max input supports harmonics filtering flexibility. |
Use Scenario: Synthesizing 2140 MHz receive LO and 1950 MHz transmit LO in residential femtocells. IC Role / Device Role / Timing Role: Dual-band LO generator using programmable prescaler and R counter for channel agility. Use Value: 3-wire interface enables FPGA-based frequency hopping; −100 dBc spurs prevent desensitization in dense indoor RF environments. |
| Wireless LAN 5 GHz Band Synthesis | Communications Test Equipment LO |
|
Use Scenario: Generating 5.15–5.825 GHz LO for 802.11a/n/ac WLAN transceivers using external active doubler. IC Role / Device Role / Timing Role: High-frequency reference source feeding multiplier chain; operates at 2.575–2.9125 GHz fundamental. Use Value: 4.0 GHz RF input capability covers entire 5 GHz band fundamentals; 55 MHz PFD max enables 10 MHz reference × 257.5 divider. |
Use Scenario: Programmable LO engine in vector signal analyzers requiring fast frequency switching and low jitter. IC Role / Device Role / Timing Role: Core frequency synthesis block in modular instrument platforms with FPGA host control. Use Value: Hardware CE pin enables microsecond-scale LO enable/disable for burst-mode testing; MUXOUT simplifies lock verification in automated test scripts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADF4153AACPZ-R7 | Higher max RF input (6.1 GHz), integrated LDO, SPI interface only - no 3-wire compatibility. | Supports mmWave bands (e.g., 5.8 GHz WiGig); requires PCB redesign for SPI routing and power sequencing. | Select when migrating to >5 GHz synthesis and higher integration; not drop-in for ADF4113BRU designs. |
| LTC6946IUF-4#PBF | 4.4 GHz max, fractional-N architecture, lower phase noise floor (−229 dBc/Hz), SPI-only interface. | Better for narrowband, low-spur applications (e.g., radar LO); lacks analog lock detect and hardware CE. | Prefer for ultra-low jitter systems where fractional-N benefits outweigh loss of 3-wire simplicity and analog lock signal. |
Compared with ADF4113BRU, ADF4153AACPZ-R7 extends frequency range and integration but sacrifices legacy interface compatibility, while LTC6946IUF-4#PBF delivers superior spectral purity at the cost of added complexity in lock monitoring and control logic.
Availability
ADF4113BRU is available at Aetrix Electronics and suitable for wireless infrastructure, test equipment, and CATV applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for ADF4113BRU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and RF ICs, serving communications, industrial, and automotive markets since 1965.
The ADF411x family was designed specifically for cost-sensitive, high-volume wireless radio LO generation - balancing performance, programmability, and ease of integration in GSM, CDMA, and WCDMA systems.
FAQ
What is the maximum RF input frequency supported by the ADF4113BRU?
The ADF4113BRU supports an RF input frequency range of 0.2 GHz to 4.0 GHz at −5 dBm input level. This specification is explicitly confirmed in Table 1 of the Rev. F datasheet under "RF Input Frequency" for ADF4113 at 5 V operation. Operation above 3.7 GHz requires −5 dBm drive level and slew rate >130 V/µs to ensure reliable prescaler triggering.
Does the ADF4113BRU support both integer-N and fractional-N synthesis?
The ADF4113BRU is an integer-N PLL synthesizer only. It uses a dual-modulus prescaler (P/P+1) with A and B counters to implement N = BP + A division. The datasheet contains no fractional modulus or sigma-delta modulator circuitry - unlike later-generation parts such as ADF4153 or ADF4351. ADF4113BRU does not support fractional-N operation.
What is the function of the VP pin on the ADF4113BRU?
The VP pin is the dedicated charge pump power supply, independent from AVDD/DVDD. It must be ≥ AVDD and ≤ 6.0 V. Setting VP = 6 V while AVDD = 3 V allows the CP output to swing up to ~5.5 V - extending VCO tuning range without requiring a separate high-voltage DC-DC converter. This is documented in the "POWER SUPPLIES" table and Figure 25–26.
Can the ADF4113BRU generate a lock detect signal without external components?
Yes. The ADF4113BRU provides both analog and digital lock detect outputs internally. The digital LOCK pin (Pin 18 in LFCSP, not present in TSSOP ADF4113BRU) and MUXOUT-configurable analog lock detect require no external comparators or timing circuits. For ADF4113BRU (TSSOP), lock status is accessed via MUXOUT with appropriate control register settings - confirmed in Figure 1 and Table 4.
Is the ADF4113BRU pin-compatible with other members of the ADF411x family?
Yes - all ADF411x variants (ADF4110/11/12/13) share identical TSSOP-16 and LFCSP-20 pinouts and register maps. The ADF4113BRU differs only in RF frequency rating (4.0 GHz vs. 550 MHz for ADF4110) and current consumption (11 mA max vs. 5.5 mA). Pin functions, timing, and interface behavior are fully compatible per Figures 3–4 and Table 4.
ADF4113BRU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF)
- PLL:
- Yes
- Input:
- CMOS, TTL
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:1
- Differential - Input:Output:
- Yes/No
- Frequency - Max:
- 4GHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-TSSOP
ADF4113BRU FAQ
1.How can I place an order for ADF4113BRU through Aetrix?
Please submit a Request for Quotation (RFQ) for ADF4113BRU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADF4113BRU reliable?
The price and inventory of ADF4113BRU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADF4113BRU is usually 5 days.
3.What payment methods are accepted for ADF4113BRU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADF4113BRU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADF4113BRU?
ADF4113BRU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADF4113BRU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADF4113BRU?
For technical support, including ADF4113BRU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADF4113BRU requirements.
6.How does Aetrix verify that ADF4113BRU is sourced from the original manufacturer or authorized distributors?
All ADF4113BRU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADF4113BRU meets industry standards.
7.What is the process for return or replacement of ADF4113BRU?
All ADF4113BRU units undergo pre-shipment inspection (PSI). If there is an issue with ADF4113BRU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADF4113BRU part is unused and in its original packaging.
Return procedure for ADF4113BRU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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