Analog Devices Inc. ADF4113HVBRUZ-RL7
- Part No.:
- ADF4113HVBRUZ-RL7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ADF4113HVBRUZ-RL7.pdf
- Description:
- IC CLK/FREQ SYNTH 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADF4113HVBRUZ-RL7 from Analog Devices is a high-voltage integer-N PLL frequency synthesizer with 15 V charge pump output, 200 MHz–4.0 GHz RF input range, and dual-modulus prescaler (8/9, 16/17, 32/33, 64/65). It drives high-tuning-voltage VCOs directly using passive loop filters in IF/RF local oscillator generation for wireless base stations and point-to-point radios.
For engineers reviewing the ADF4113HVBRUZ-RL7 datasheet, ADF4113HVBRUZ-RL7 pinout, ADF4113HVBRUZ-RL7 application, or ADF4113HVBRUZ-RL7 equivalent, key selection criteria include charge pump voltage compliance (13.5–16.5 V), programmable ICP (80 µA / 640 µA), digital lock detect precision (3 ns or 10 ns), and TSSOP-16 package compatibility with ADF4110/ADF4111/ADF4112/ADF4113 family designs.
Technical Context
The ADF4113HVBRUZ-RL7 integrates a low-noise phase frequency detector (PFD), precision high-voltage charge pump, 14-bit R counter, 13-bit B/6-bit A counters, and dual-modulus prescaler (P/P+1) to realize N = BP + A division. Its PFD includes programmable antibacklash pulse width (7.2 ns only) to eliminate dead zone and minimize reference spurs.
It supports 3-wire serial interface (CLK/DATA/LE) with 24-bit shift register, latch-select control bits (C2/C1), and MUXOUT multiplexer for accessing internal signals including digital lock detect, N/R divider outputs, or analog lock detect. Power-down is controlled via CE pin or software bit F2 in function latch.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Input Range | 200 MHz to 4.0 GHz - supports VCO tuning across cellular, microwave, and test equipment bands |
| Charge Pump Voltage (VP) | 13.5 V to 16.5 V - enables direct drive of high-voltage VCOs without active loop filter |
| Charge Pump Current (ICP) | 80 µA or 640 µA - selectable via CPI3:CPI1 bits; sets loop filter gain and settling time |
| PFD Frequency Max | 5 MHz - constrains reference frequency division ratio and loop bandwidth design |
| Digital Lock Detect Precision | 3 ns or 10 ns window - configurable via LDP bit; determines lock acquisition reliability under jitter |
| Operating Temp Range | −40°C to +85°C - qualified for industrial-grade wireless infrastructure deployment |
| Supply Voltage (AVDD/DVDD) | 2.7 V to 5.5 V - single-supply operation compatible with 3.3 V or 5 V logic domains |
Pinout & Package
TSSOP-16 package with exposed thermal pad (EPAD) requiring connection to AGND per datasheet Figure 3 and Table 5. Pin count and layout match ADF4110/ADF4111/ADF4112/ADF4113 family for drop-in replacement in existing designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RSET (Pin 1) | Charge pump current setting | Resistor to CPGND sets ICPmax = 3/RSET; 4.7 kΩ yields 640 µA typical |
| CP (Pin 2) | Charge pump output | ±ICP source/sink to external loop filter; requires decoupling near VP rail |
| CPGND (Pin 3) | Charge pump ground return | Separate low-impedance path for CP current; must be isolated from DGND/AGND planes |
| RFINA/RFINB (Pins 5–6) | RF prescaler differential input | AC-coupled CMOS inputs accepting up to 3.7 GHz; RFINB requires 100 pF bypass |
| REFIN (Pin 8) | Reference clock input | CMOS/TTL-compatible; 5–150 MHz range; biased at AVDD/2 with 100 kΩ input resistance |
| CE (Pin 10) | Chip enable | Asynchronous hardware power-down; forces CP into three-state and disables all counters |
| CLK/DATA/LE (Pins 11–13) | 3-wire serial interface | MSB-first 24-bit load; LE rising edge transfers data to selected latch (R/N/function) |
| MUXOUT (Pin 14) | Multiplexer output | Configurable via M3:M1 bits to output lock detect, N/R divider, SDOUT, or DGND |
| VP (Pin 16) | Charge pump power supply | 13.5–16.5 V rail; must be independently decoupled with low-ESR capacitors |
Key Features
| Feature | Design Value |
|---|---|
| High-voltage charge pump | 15 V output capability eliminates need for active loop filter when driving >10 V VCOs |
| Programmable charge pump current | Two discrete ICP settings (80 µA / 640 µA) allow optimization of loop stability vs. lock time |
| Digital lock detect | Configurable 3 ns or 10 ns phase error threshold ensures reliable lock indication in noisy environments |
| Pin compatibility | Direct replacement for ADF4110/ADF4111/ADF4112/ADF4113 in TSSOP-16 footprint |
| Three-wire serial interface | 24-bit shift register with latch-select control bits enables compact microcontroller interfacing |
Applications
| Wireless Base Station LO | Point-to-Point Radio LO |
|---|---|
Use Scenario: Generating stable local oscillator signals for up/downconversion in 4G/LTE macrocell and small cell base stations. IC Role / Device Role / Timing Role: Integer-N PLL synthesizer providing precise RF frequency synthesis with low phase noise and fast lock time. Use Value: 15 V charge pump drives high-Q VCOs directly, reducing component count and improving phase noise floor vs. active-filter solutions. | Use Scenario: Providing tunable LO for licensed-band (e.g., 6–42 GHz) backhaul radios operating in harsh outdoor environments. IC Role / Device Role / Timing Role: High-reliability frequency synthesizer supporting wideband VCO tuning with industrial temperature range (−40°C to +85°C). Use Value: Dual-modulus prescaler (8/9 to 64/65) enables flexible N-divider configuration across multi-GHz bands without sacrificing resolution. |
| ADC/DAC Clock Generation | Communications Test Equipment |
Use Scenario: Delivering low-jitter sampling clocks to high-speed analog-to-digital and digital-to-analog converters in instrumentation systems. IC Role / Device Role / Timing Role: Low-phase-noise PLL core generating clean clock signals referenced to stable crystal oscillators. Use Value: −212 dBc/Hz normalized phase noise floor minimizes sampling clock jitter, preserving ENOB in >10-bit converters. | Use Scenario: Enabling agile frequency synthesis in signal analyzers, vector network analyzers, and RF signal generators. IC Role / Device Role / Timing Role: Programmable synthesizer supporting rapid frequency hopping and fine resolution via 14-bit R and 19-bit N dividers. Use Value: MUXOUT-configurable lock detect and divider outputs simplify system-level synchronization and diagnostics during calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PLL synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADF4113BRUZ | Standard-voltage version (5 V max VP); no high-voltage charge pump | Restricted to ≤5 V VCOs; cannot replace ADF4113HVBRUZ-RL7 in high-tuning-voltage designs | Select only when VCO tuning voltage ≤5 V and loop filter is active or charge pump voltage headroom is sufficient |
| ADF4153BRUZ | Fractional-N architecture; integrated ΣΔ modulator; lower phase noise floor (−222 dBc/Hz) | Supports finer frequency resolution and faster settling but requires more complex loop filter design | Choose when sub-Hz frequency step size or <100 µs lock time is required; not drop-in compatible due to different register map |
Compared with ADF4113BRUZ and ADF4153BRUZ, the ADF4113HVBRUZ-RL7 uniquely delivers 15 V charge pump output for passive-loop VCO drive-enabling simpler, lower-noise RF front-ends where high tuning voltage is mandatory.
Availability
ADF4113HVBRUZ-RL7 is available at Aetrix Electronics and suitable for wireless infrastructure, point-to-point radio, and high-performance test equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for ADF4113HVBRUZ-RL7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and RF ICs, serving precision instrumentation, communications, and industrial markets since 1965.
The ADF4113HVBRUZ-RL7 belongs to Analog Devices' PLL frequency synthesizer product line, designed specifically for high-voltage VCO drive in wireless infrastructure and test equipment where passive loop filters and simplified board layout are critical.
FAQ
What is the maximum RF input frequency supported by the ADF4113HVBRUZ-RL7?
The ADF4113HVBRUZ-RL7 supports an RF input frequency range of 200 MHz to 4.0 GHz. At 5 V supply, the upper limit is confirmed at 4.0 GHz with −5 dBm input level; at 3 V, the maximum is 3.7 GHz. The prescaler output must remain ≤200 MHz, so prescaler selection (e.g., 16/17 for 2 GHz input) is required to meet this constraint. This specification is verified in Table 1 of the Rev. B datasheet.
Does the ADF4113HVBRUZ-RL7 require an external active loop filter?
No, the ADF4113HVBRUZ-RL7 does not require an external active loop filter. Its 15 V charge pump (VP = 13.5–16.5 V) enables direct drive of high-tuning-voltage VCOs using passive loop filters-reducing component count, power consumption, and noise contribution. This capability is explicitly stated in the General Description and validated in application circuits using Sirenza VCO190-1500T(Y) on EV-ADF4113HVSDZ1 evaluation board.
How is the charge pump current configured on the ADF4113HVBRUZ-RL7?
The ADF4113HVBRUZ-RL7 charge pump current is configured via the CPI3:CPI1 bits in the function latch (Figure 22). Two settings are available: 80 µA (CPI3:CPI1 = 000) and 640 µA (CPI3:CPI1 = 111), with nominal accuracy of ±2.5%. The RSET pin connects to CPGND through a resistor (e.g., 4.7 kΩ) to set ICPmax = 3/RSET, as defined in Table 5 and Figure 13.
Is the ADF4113HVBRUZ-RL7 pin-compatible with other ADF411x devices?
Yes, the ADF4113HVBRUZ-RL7 is pin-compatible with ADF4110, ADF4111, ADF4112, ADF4113, ADF4106, and ADF4002 synthesizers in TSSOP-16 package. Pin functions-including RSET, CP, CPGND, RFINA/B, REFIN, CE, CLK, DATA, LE, MUXOUT, and VP-are identical. This allows direct substitution in existing layouts, though VP voltage requirements (13.5–16.5 V) must be verified in the target design.
What is the purpose of the MUXOUT pin on the ADF4113HVBRUZ-RL7?
The MUXOUT pin on the ADF4113HVBRUZ-RL7 provides access to internal signals via a 3-bit control (M3:M1). Configurable outputs include digital lock detect (active high), analog lock detect (open-drain), N-divider output, R-divider output, SDOUT, DVDD, or DGND. This enables real-time lock monitoring, loop diagnostics, and system synchronization without additional probing-functionality confirmed in Figure 18 and Table 5 of the datasheet.
ADF4113HVBRUZ-RL7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Clock/Frequency Synthesizer (RF)
- PLL:
- Yes
- Input:
- CMOS, TTL
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:1
- Differential - Input:Output:
- Yes/No
- Frequency - Max:
- 4GHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-TSSOP
ADF4113HVBRUZ-RL7 FAQ
1.How can I place an order for ADF4113HVBRUZ-RL7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADF4113HVBRUZ-RL7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADF4113HVBRUZ-RL7 reliable?
The price and inventory of ADF4113HVBRUZ-RL7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADF4113HVBRUZ-RL7 is usually 5 days.
3.What payment methods are accepted for ADF4113HVBRUZ-RL7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADF4113HVBRUZ-RL7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADF4113HVBRUZ-RL7?
ADF4113HVBRUZ-RL7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADF4113HVBRUZ-RL7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADF4113HVBRUZ-RL7?
For technical support, including ADF4113HVBRUZ-RL7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADF4113HVBRUZ-RL7 requirements.
6.How does Aetrix verify that ADF4113HVBRUZ-RL7 is sourced from the original manufacturer or authorized distributors?
All ADF4113HVBRUZ-RL7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADF4113HVBRUZ-RL7 meets industry standards.
7.What is the process for return or replacement of ADF4113HVBRUZ-RL7?
All ADF4113HVBRUZ-RL7 units undergo pre-shipment inspection (PSI). If there is an issue with ADF4113HVBRUZ-RL7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADF4113HVBRUZ-RL7 part is unused and in its original packaging.
Return procedure for ADF4113HVBRUZ-RL7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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