Analog Devices Inc. AD-FMCJESDADC1-EBZ

Overview

AD-FMCJESDADC1-EBZ from Analog Devices is a high-speed FMC-compliant evaluation board featuring two AD9250 dual-channel 14-bit ADCs for 4-channel simultaneous data acquisition at up to 250 MSPS, with JESD204B serial interface, on-board AD9517-1 clock generator, and external trigger input - used in RF test equipment, radar prototyping, and software-defined radio development.

For engineers reviewing the AD-FMCJESDADC1-EBZ datasheet, AD-FMCJESDADC1-EBZ pinout, AD-FMCJESDADC1-EBZ application, or AD-FMCJESDADC1-EBZ equivalent, this page delivers verified hardware specifications, carrier compatibility (ML605/KC705/VC707/ZC706), FPGA reference design support, JESD204B lane-level signal mapping, and ADC sample rate configuration guidance.

Technical Context

The AD-FMCJESDADC1-EBZ implements a dual-AD9250 architecture delivering four synchronized 14-bit ADC channels via JESD204B subclass 1 links, each operating at up to 250 MSPS with configurable sampling rates from 40 MHz to 250 MHz. It integrates an AD9517-1 clock distributor providing sub-picosecond jitter performance and supporting internal PLL/VCO or external reference locking.

Reference designs use Xilinx MicroBlaze-based systems with AXI-Lite controlled pcores: one JESD core and two AD9250-specific pcores handling capture, PN9/PN23 monitoring, and DMA transfer to external DDR-DRAM. The board supports SYSREF-synchronized multi-board operation and includes GTX transceiver-level debug visibility for CGS, ILAS, and data phases.

Key Specifications

Availability

AD-FMCJESDADC1-EBZ is available at Aetrix Electronics and suitable for RF instrumentation, radar signal processing, SDR baseband development, and high-speed test equipment requiring stable component supply and long-term reference design continuity.

Supply support for AD-FMCJESDADC1-EBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and high-speed data conversion.

The AD-FMCJESDADC1-EBZ belongs to Analog Devices' FMC-based evaluation platform family, designed to accelerate prototyping of JESD204B-enabled high-speed data acquisition systems with Xilinx FPGAs.

FAQ

What is the primary function of the AD-FMCJESDADC1-EBZ?

The AD-FMCJESDADC1-EBZ is a reference evaluation board-not an IC or discrete component-that provides a complete, FPGA-ready hardware platform for capturing high-speed analog signals using two AD9250 ADCs. It enables rapid validation of JESD204B data paths, clock synchronization, and system-level integration with Xilinx 7-series FPGAs. The AD-FMCJESDADC1-EBZ does not perform signal conversion itself but hosts and interfaces the ADCs and clocking circuitry required for such tasks.

Which FPGA carriers are compatible with the AD-FMCJESDADC1-EBZ?

The AD-FMCJESDADC1-EBZ is validated for use with ML605, KC705, VC707, and ZC706 carrier boards via their FMC-HPC connectors. All supported carriers provide full access to the required GTX transceivers, clock inputs, and AXI interconnect resources. The AD-FMCJESDADC1-EBZ requires HPC (not LPC) due to its JESD204B lane count and clock routing needs - KC705's partially populated HPC limits DAC functionality but fully supports the AD-FMCJESDADC1-EBZ's ADC-only operation.

Does the AD-FMCJESDADC1-EBZ include DAC functionality?

No, the AD-FMCJESDADC1-EBZ is ADC-only: it integrates two AD9250 converters (four total channels) and omits the AD9129 DACs found on the similar FMC-176 board. Reference designs include DAC pcores for compatibility, but users must explicitly disable or ignore them when deploying the AD-FMCJESDADC1-EBZ. The AD-FMCJESDADC1-EBZ's hardware contains no DAC components, and its signal paths, layout, and power delivery are optimized exclusively for high-fidelity ADC acquisition.

What clocking architecture does the AD-FMCJESDADC1-EBZ use?

The AD-FMCJESDADC1-EBZ uses the AD9517-1 clock generator to provide low-jitter sampling clocks (up to 250 MHz) to both AD9250s and configurable reference clocks to the host FPGA. The AD9517-1 supports internal PLL/VCO operation locked to an external 10 MHz reference or direct external clock injection. Its outputs meet JESD204B subclass 1 timing requirements for deterministic latency and multi-device synchronization - critical for coherent multi-board acquisition using the AD-FMCJESDADC1-EBZ.

How is data captured and transferred from the AD-FMCJESDADC1-EBZ?

Data from the AD-FMCJESDADC1-EBZ flows through the JESD204B interface into a Xilinx JESD core, then into two AD9250-specific pcores that buffer samples and initiate DMA transfers to external DDR-DRAM via the host FPGA's memory controller. Capture is software-triggered, with status flags (overflow, out-of-range) reported back over AXI-Lite. The AD-FMCJESDADC1-EBZ reference design includes UART-based control, Chipscope debug visibility, and prebuilt bitfiles for immediate validation without FPGA toolchain setup.