Analog Devices Inc. ADG3123BRUZ

Overview

ADG3123BRUZ from Analog Devices is an 8-channel noninverting CMOS-to-high-voltage level translator with input voltage range 2.3 V to 5.5 V, output voltage capability from −24.2 V to +35 V, typical propagation delay of 80 ns, rise/fall times of 12 ns/19.5 ns, and ultralow quiescent current of 65 μA. It serves as a logic-level interface between low-voltage timing controllers and high-voltage TFT-LCD panel drivers.

For engineers reviewing the ADG3123BRUZ datasheet, ADG3123BRUZ pinout, ADG3123BRUZ application, or ADG3123BRUZ equivalent, this device supports dual-supply high-voltage translation (VDDA ≤ VDDB, VDDB–VSS ≤ 35 V), features channel-specific output voltage assignment (Y1–Y6 referenced to VDDA; Y7–Y8 to VDDB), and operates across −40°C to +85°C in a RoHS-compliant 20-lead TSSOP package.

Technical Context

The ADG3123BRUZ uses an enhanced LC2MOS process to enable high-voltage operation while maintaining ultralow power consumption. Its internal architecture separates output voltage referencing: VDDA sets high-level outputs for Y1–Y6, VDDB sets high-level outputs for Y7–Y8, and VSS defines the common low-level output for all eight channels.

Operation requires strict supply sequencing-VDDB and VSS must be powered before A1–A8 inputs-and enforces VDDB ≥ VDDA and |VDDB − VSS| ≤ 35 V. The device delivers fast switching (12 ns rise, 19.5 ns fall) into capacitive loads up to 4.1 nF at 20 kHz, with output impedance of 30 Ω enabling robust drive capability.

Key Specifications

Pinout & Package

ADG3123BRUZ is housed in a 20-lead, Pb-free, RoHS-compliant TSSOP package (JEDEC MO-153-AC, RU-20 footprint).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage level translation applications.

Compared with ADG3123BRUZ, ADG3123BRUZ-REEL7 offers identical performance in optimized packaging for production, while MAX13202EASA+ trades dual-rail flexibility and ultralow power for simpler supply architecture - making ADG3123BRUZ the preferred choice for multi-rail TFT-LCD and precision piezo systems.

Availability

ADG3123BRUZ is available at Aetrix Electronics and suitable for TFT-LCD panel interfaces, piezoelectric motor drivers, and industrial HMI display subsystems requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.

Supply support for ADG3123BRUZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide.

The ADG3123BRUZ belongs to Analog Devices' high-voltage interface product line, engineered specifically for translating low-voltage logic to bipolar high-voltage domains in flat-panel displays, precision motion control, and industrial automation systems.

FAQ

What is the maximum allowable voltage difference between VDDB and VSS for ADG3123BRUZ?

The ADG3123BRUZ specifies an absolute maximum rating of 44 V between VDDB and VSS, but the recommended operating limit is ≤35 V per the datasheet's "Power Supply Voltages" table and General Description. Exceeding 35 V risks violating the device's safe operating area and may cause premature failure. Always maintain VDDB ≥ VDDA and verify that |VDDB − VSS| ≤ 35 V under all operating conditions, including transients.

Can ADG3123BRUZ translate 2.3 V logic inputs to −24.2 V / +35 V outputs?

Yes, ADG3123BRUZ supports input voltages from 2.3 V to 5.5 V and delivers output voltage levels down to −24.2 V (low) and up to +35 V (high), as confirmed in the Features and Specifications sections. The low-level output is set by VSS, and the high-level output depends on VDDA (for Y1–Y6) or VDDB (for Y7–Y8). Input threshold levels (VIH = 1.7 V min, VIL = 0.8 V max) ensure reliable recognition of 2.3 V logic.

Is ADG3123BRUZ pin-compatible with ADG3123BRUZ-REEL7?

Yes, ADG3123BRUZ and ADG3123BRUZ-REEL7 share identical die, pinout, electrical specifications, and 20-lead TSSOP (RU-20) package dimensions. The only difference is packaging format: ADG3123BRUZ is supplied in tube packaging, while ADG3123BRUZ-REEL7 is supplied on a 7-inch tape-and-reel (2500 units per reel) for automated assembly. No PCB or schematic changes are needed when substituting between them.

What decoupling capacitors are recommended for ADG3123BRUZ power pins?

Analog Devices recommends placing a 10 µF bulk capacitor and a 0.1 µF ceramic capacitor in parallel on each of VDDB, VDDA, and VSS pins, located as close as possible to the respective package pins. This configuration suppresses both low-frequency ripple and high-frequency noise, ensuring stable high-voltage output switching and minimizing propagation delay variation. Layout best practice requires short, low-inductance traces between capacitors and pins.

Does ADG3123BRUZ require specific power-up sequencing?

Yes, ADG3123BRUZ requires strict power-up sequencing: VDDB and VSS must be fully established before applying any signal to A1–A8 inputs or VDDA. This prevents latch-up and undefined output states. The datasheet explicitly states "power up the ADG3123 first (VDDB and VSS) before applying the signals to its inputs." Failure to follow this sequence may result in excessive current draw or temporary malfunction.