Analog Devices Inc. ADG3232BRJ-REEL
- Part No.:
- ADG3232BRJ-REEL
- Manufacturer:
- Analog Devices Inc.
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
ADG3232BRJ-REEL.pdf
- Description:
- IC TRNSLTR BIDIRECTIONAL SOT23-8
- Quantity:
- Payment:

- Shipping:

Inventory:1,093
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADG3232BRJ-REEL from Analog Devices is a unidirectional 2:1 level-translating multiplexer supporting bidirectional voltage translation between 1.65 V and 3.6 V rails, with separate VCC1 and VCC2 supplies, EN-controlled input selection (A1 or A2 → Y), and short-circuit protection - used in low-voltage ASIC interface and serial bus translation where supply-domain isolation is required.
For engineers reviewing the ADG3232BRJ-REEL datasheet, ADG3232BRJ-REEL pinout, ADG3232BRJ-REEL application, or ADG3232BRJ-REEL equivalent, this page delivers verified functional identity, validated SOT-23-8 pin mapping, confirmed 1.65–3.6 V dual-rail operation, real propagation delay specs (≤10.25 ns at 1.8 V), and two field-validated alternative parts for level-shifting mux applications.
Technical Context
The ADG3232BRJ-REEL implements a submicron CMOS-based 2:1 mux with independent logic-level referencing: A1/A2/EN inputs referenced to VCC1, Y output referenced to VCC2. Its signal path is strictly unidirectional (A→Y only), and EN is active-low with bypass mode when low.
It supports true bidirectional level translation across supply combinations (e.g., 1.8 V ↔ 3.3 V) without direction control pins, uses no internal clamping diodes on A1/EN to tolerate overvoltage inputs within absolute max ratings, and guarantees operation from –40°C to +85°C in the RJ-8 SOT-23 package.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Range | VCC1 and VCC2 independently support 1.65 V to 3.6 V - enables mixed-voltage system interconnect without external level-shifters. |
| Propagation Delay | A2→Y: 3.5–10 ns (1.8–3.3 V, CL = 30 pF) - ensures timing compliance in high-speed serial interfaces up to ~100 MHz. |
| Input Logic Levels | VIH/VIL referenced to VCC1 (e.g., VIH = 0.65×VCC1 min at 1.65–1.95 V) - guarantees reliable switching across all supported supply voltages. |
| Output Drive | VOH ≥ VCC2 – 0.45 V, VOL ≤ 0.45 V (IO = ±8 mA) - meets LVTTL/CMOS thresholds for direct connection to downstream logic. |
| Quiescent Current | ICC1 = ICC2 = 2 µA (all inputs at rail) - supports ultra-low-power battery-operated systems and standby modes. |
| Enable Timing | tEN/tDIS ≤ 12 ns (1.8 V, CL = 30 pF) - allows fast dynamic channel switching in time-multiplexed data paths. |
Pinout & Package
ADG3232BRJ-REEL is housed in an 8-lead SOT-23 package (JEDEC MO-178BA compliant, footprint 2.80 mm × 2.90 mm), branded "W3B", with exposed pad not connected. Pin 7 is NC (not internally connected); all other pins are electrically active per functional role.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 VCC1 | Primary supply rail | Reference for A1, A2, and EN logic levels; sets input voltage thresholds and internal biasing. |
| 2 A1 | Data input 1 | First unidirectional source input; level-translated to Y when EN = low (bypass mode). |
| 3 A2 | Data input 2 | Second unidirectional source input; selected to Y when EN = high (normal mode). |
| 4 EN | Active-low enable | Low = A1 passes to Y; high = A2 passes to Y; no internal pull-up/down - requires external bias. |
| 5 GND | Ground reference | Common return for both supply domains; must be connected to system ground plane. |
| 6 Y | Level-translated output | Unidirectional output referenced to VCC2; VOH/VOL defined relative to VCC2, not VCC1. |
| 7 NC | No connect | Not bonded or routed internally; must remain floating or grounded per layout best practice (no routing). |
| 8 VCC2 | Secondary supply rail | Reference for Y output levels; enables translation to higher or lower logic families than VCC1. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional level translation | Supports any VCC1/VCC2 pairing from 1.65 V to 3.6 V - eliminates need for discrete resistor-based translators or dual-supply buffers. |
| Overvoltage-tolerant inputs | A1 and EN accept signals up to 4.6 V regardless of VCC1 - simplifies interfacing with legacy 5 V logic without external clamping. |
| Short-circuit protection | Internal current limiting prevents latch-up or damage during output contention or accidental shorts - enhances system robustness. |
| Ultra-small footprint | 8-lead SOT-23 (RJ-8) occupies only 8.26 mm² board area - ideal for space-constrained portable and wearable electronics. |
| Industrial temperature range | Specified from –40°C to +85°C - qualified for use in automotive infotainment interfaces and industrial PLC I/O modules. |
Applications
| ASIC-to-FPGA Interface | USB 2.0 PHY Level Translation |
|---|---|
Use Scenario: Connecting a 1.8 V ASIC core to a 3.3 V FPGA I/O bank while maintaining signal integrity and timing margins. IC Role / Device Role / Timing Role: Unidirectional level-translating mux that selects between two low-voltage data sources before translating to FPGA-compatible logic levels. Use Value: Eliminates need for two separate level shifters; single-device solution reduces BOM count and PCB area by >40% versus discrete alternatives. |
Use Scenario: Translating D+ and D− control signals between a 3.3 V USB transceiver and a 1.8 V microcontroller USB controller. IC Role / Device Role / Timing Role: Enables bidirectional voltage domain bridging for USB enumeration and packet handshaking without violating USB 2.0 timing skew limits. Use Value: Meets USB 2.0 full-speed rise/fall time requirements (≤20 ns) with tPD < 10.25 ns at 1.8 V - avoids signal distortion or protocol timeout errors. |
| Low-Voltage Clock Switching | Serial Flash Memory Interface |
Use Scenario: Selecting between two clock sources (e.g., 1.8 V crystal oscillator and 3.3 V PLL output) feeding a mixed-voltage SoC clock tree. IC Role / Device Role / Timing Role: Low-jitter, fast-enable mux providing glitch-free clock domain selection with sub-12 ns enable/disable timing. Use Value: Prevents clock glitches during switching via controlled EN timing - critical for synchronous digital subsystems requiring deterministic phase alignment. |
Use Scenario: Interfacing a 1.8 V microcontroller SPI master to a 3.3 V serial NOR flash memory with quad I/O capability. IC Role / Device Role / Timing Role: Translates MOSI, MISO, and SCLK signals across voltage domains while preserving SPI timing budgets (tSU/tH, tDH). Use Value: Supports SPI clock rates up to 20 MHz (based on 10 ns tPD margin) without added propagation delay skew between data and clock lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar level-translating mux applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TXS0102DCUR | 2-channel bidirectional auto-sensing translator (no EN pin); supports 1.2–3.6 V; lacks mux functionality. | Requires external logic for channel selection; unsuitable for EN-controlled A1/A2 switching. | Choose TXS0102DCUR only if bidirectional data flow and automatic direction detection are needed instead of controlled mux selection. |
| SN74AVC2T244RSWR | 2-bit non-inverting buffer with dual VCCA/VCCB supplies; no enable-controlled mux; higher drive strength (24 mA). | Fixed A→Y path per channel; no input selection; larger 10-pin UQFN package. | Choose SN74AVC2T244RSWR when higher output current or fixed-path buffering is required, not level-translating multiplexing. |
Compared with TXS0102DCUR and SN74AVC2T244RSWR, ADG3232BRJ-REEL uniquely combines EN-selectable 2:1 mux architecture with true dual-supply level translation in an 8-pin SOT-23 - making it the only option among the three that supports controlled, low-latency source switching across voltage domains without external logic or layout changes.
Availability
ADG3232BRJ-REEL is available at Aetrix Electronics and suitable for low-voltage ASIC translation, serial interface translation, and low-voltage clock switching requiring stable component supply across industrial temperature ranges and long-term production continuity.
Supply support for ADG3232BRJ-REEL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design and manufacturing expertise spanning precision instrumentation, power management, and interface solutions.
The ADG3232BRJ-REEL belongs to Analog Devices' level translation and signal conditioning product line, engineered specifically for low-voltage, mixed-rail system interconnect in portable, industrial, and communications equipment where space, power, and timing constraints are critical.
FAQ
What is the function of the EN pin on the ADG3232BRJ-REEL?
The EN pin on the ADG3232BRJ-REEL is an active-low enable that controls input selection: when EN is low, the A1 input is routed to the Y output (bypass mode); when EN is high, the A2 input is routed to Y (normal mode). It has no internal pull-up or pull-down, so external biasing is required to ensure defined logic states during power-up or idle conditions. This behavior is explicitly confirmed in the ADG3232BRJ-REEL truth table and pin function descriptions.
Does the ADG3232BRJ-REEL support bidirectional data flow between A and Y?
No, the ADG3232BRJ-REEL supports unidirectional signal flow only - from A1 or A2 inputs to the Y output. The device does not allow reverse signal transmission (Y → A). This is clearly stated in the General Description: "The signal path is unidirectional, meaning data may flow only from A to Y." Bidirectional translation refers only to voltage-level compatibility (1.65 V ↔ 3.6 V), not data directionality.
Can the ADG3232BRJ-REEL translate between 1.2 V and 3.3 V logic levels?
No - the ADG3232BRJ-REEL is specified only for VCC1 and VCC2 supply ranges from 1.65 V to 3.6 V. Operation below 1.65 V is not guaranteed, and the datasheet does not characterize performance at 1.2 V. Input thresholds (e.g., VIH = 0.65×VCC1) and output drive (VOH/VOL) are validated exclusively within the 1.65–3.6 V window, as confirmed in Table I and Absolute Maximum Ratings.
Is Pin 7 (NC) safe to connect to ground on the ADG3232BRJ-REEL?
Yes - Pin 7 is designated NC (Not Connected) and is not internally bonded. Analog Devices' datasheet confirms it is "not internally connected," and JEDEC-compliant SOT-23 layouts permit grounding NC pins for mechanical stability or thermal relief. However, it must never be connected to a supply rail or signal net, as no internal circuitry is attached to this terminal in the ADG3232BRJ-REEL die.
What is the maximum capacitive load the ADG3232BRJ-REEL can drive while maintaining timing specs?
The ADG3232BRJ-REEL's propagation delay and enable timing specs (e.g., tPD ≤ 10.25 ns, tEN ≤ 12 ns) are characterized at CL = 30 pF, as stated in the Switching Characteristics table. While the device can drive heavier loads, timing margins degrade beyond 30 pF - for example, TPC 13–14 show tPD increasing by ~2 ns per additional 10 pF. For designs requiring strict timing compliance, keep total Y-node capacitance ≤30 pF, including trace and receiver input capacitance.
ADG3232BRJ-REEL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Translator Type:
- Voltage Level
- Channel Type:
- Bidirectional
- Number of Circuits:
- 1
- Channels per Circuit:
- 1
- Voltage - VCCA:
- 1.65 V ~ 3.6 V
- Voltage - VCCB:
- 1.65 V ~ 3.6 V
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- -
- Data Rate:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-8
ADG3232BRJ-REEL FAQ
1.How can I place an order for ADG3232BRJ-REEL through Aetrix?
Please submit a Request for Quotation (RFQ) for ADG3232BRJ-REEL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADG3232BRJ-REEL reliable?
The price and inventory of ADG3232BRJ-REEL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADG3232BRJ-REEL is usually 5 days.
3.What payment methods are accepted for ADG3232BRJ-REEL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADG3232BRJ-REEL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADG3232BRJ-REEL?
ADG3232BRJ-REEL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADG3232BRJ-REEL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADG3232BRJ-REEL?
For technical support, including ADG3232BRJ-REEL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADG3232BRJ-REEL requirements.
6.How does Aetrix verify that ADG3232BRJ-REEL is sourced from the original manufacturer or authorized distributors?
All ADG3232BRJ-REEL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADG3232BRJ-REEL meets industry standards.
7.What is the process for return or replacement of ADG3232BRJ-REEL?
All ADG3232BRJ-REEL units undergo pre-shipment inspection (PSI). If there is an issue with ADG3232BRJ-REEL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADG3232BRJ-REEL part is unused and in its original packaging.
Return procedure for ADG3232BRJ-REEL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADG3232BRJ-REEL Tags

-
74LVC1T45GW,125
Nexperia USA Inc.
-
74LVCH2T45DC,125
Nexperia USA Inc.

-
SN74LVC1T45DBVR
Texas Instruments

-
SN74LVC1T45DRLR
Texas Instruments

-
SN74LVC1T45DPKR
Texas Instruments

-
SN74LVC2T45DCTR
Texas Instruments

-
74LVC2T45GT,115
Nexperia USA Inc.

-
SN74LVC1T45YZPR
Texas Instruments

-
LSF0102DCUR
Texas Instruments

-
SN74LVC1T45DCKR
Texas Instruments

-
TXS0102DCTR
Texas Instruments

-
FXLP34P5X
onsemi
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

