Analog Devices Inc. ADG3247BCPZ
- Part No.:
- ADG3247BCPZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 40-VFQFN Exposed Pad, CSP
- Datasheet:
-
ADG3247BCPZ.pdf
- Description:
- IC BUS SWITCH 8 X 1:1 40LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:4,632
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Product details
Overview
ADG3247BCPZ from Analog Devices is a dual-supply, 8-bit bidirectional logic level translator with auto-direction sensing, supporting 1.65 V to 3.6 V on both A- and B-side I/Os, 3.6 V tolerant inputs, and 24 mA drive capability per channel - used in mixed-voltage interfacing between FPGA I/O banks and legacy 3.3 V peripherals.
For engineers reviewing the ADG3247BCPZ datasheet, ADG3247BCPZ pinout, ADG3247BCPZ application, or ADG3247BCPZ equivalent, key selection criteria include voltage translation range, direction-sensing latency, channel count, drive strength, and LFCSP-20 package compatibility with high-density PCB layouts.
Technical Context
The ADG3247BCPZ implements an auto-direction-detection architecture using internal weak pull-up/pull-down biasing and edge-triggered direction latching, enabling transparent bidirectional data flow without external direction control signals. It supports simultaneous translation across eight independent channels with propagation delays under 3.5 ns (typ) at 3.3 V supply.
Each channel features independent A- and B-side I/Os with rail-to-rail input voltage ranges (1.65 V to 3.6 V), 3.6 V overvoltage-tolerant inputs on both sides, and output drive capable of sinking or sourcing up to 24 mA while maintaining VOL ≤ 0.4 V and VOH ≥ 0.8 × VCC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channel Count | 8 independent bidirectional channels - enables full-byte parallel level translation without external direction lines. |
| VCCA / VCCB Range | 1.65 V to 3.6 V - supports mixed-voltage interconnect between 1.8 V/2.5 V/3.3 V domains. |
| Propagation Delay | 3.5 ns (typ) at 3.3 V - suitable for high-speed interfaces up to ~100 MHz data rates. |
| Output Drive Strength | ±24 mA per channel - drives standard CMOS loads and short PCB traces without external buffers. |
| Input Tolerance | 3.6 V tolerant on both A and B sides - allows safe connection to higher-voltage buses without clamping diodes. |
| Package | 20-lead LFCSP (4 mm × 4 mm, 0.5 mm pitch) - compact footprint for space-constrained FPGA/ASIC interface designs. |
Pinout & Package
The ADG3247BCPZ is housed in a 20-lead Lead Frame Chip Scale Package (LFCSP) with exposed thermal pad, optimized for low-inductance signal paths and thermal dissipation in dense digital systems.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A7 | A-side bidirectional I/O | Connects to lower-voltage domain (e.g., 1.8 V FPGA bank); auto-senses data direction per channel. |
| B0–B7 | B-side bidirectional I/O | Connects to higher-voltage domain (e.g., 3.3 V peripheral bus); tolerates up to 3.6 V regardless of VCCB. |
| VCCA | A-side supply | Supplies core logic and A-side I/Os; must be 1.65 V to 3.6 V; decoupling required near pin. |
| VCCB | B-side supply | Supplies B-side I/Os only; independent of VCCA; enables true dual-supply operation. |
| GND | Ground reference | Common return for both supplies; connects to exposed thermal pad for thermal and EMI performance. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-direction sensing | Eliminates need for external DIR control line - reduces PCB routing complexity and FPGA pin count. |
| Rail-to-rail I/O voltage range | Supports 1.65 V to 3.6 V on both sides - enables flexible voltage domain bridging without redesign. |
| 3.6 V tolerant inputs | Allows direct connection to 3.3 V buses even when VCCA = 1.8 V - avoids external protection circuitry. |
| Low propagation delay | 3.5 ns typical - preserves timing margins in high-speed parallel interfaces like memory-mapped I/O or GPIO expansion. |
Applications
| Industrial PLC I/O Expansion | FPGA-to-ADC Interface |
|---|---|
Use Scenario: Interfacing 1.8 V FPGA GPIO banks to 3.3 V industrial analog input modules with isolated power rails. IC Role / Device Role / Timing Role: Bidirectional level translator enabling real-time sensor data readback and configuration writes across voltage domains. Use Value: Eliminates discrete MOSFET translators and direction-control logic, reducing BOM count by 4+ components per byte. | Use Scenario: Connecting a 2.5 V FPGA I/O bank to a 3.3 V SAR ADC's parallel data bus and control lines. IC Role / Device Role / Timing Role: Synchronizing 8-bit parallel ADC output reads and conversion start commands across voltage boundaries. Use Value: Maintains sub-5 ns channel-to-channel skew, preserving ADC sampling integrity at >10 MSPS rates. |
| Automotive Infotainment Debug Port | Medical Imaging Sensor Hub |
Use Scenario: Bridging 1.8 V SoC debug UART/GPIO to 3.3 V legacy CAN transceiver diagnostics interface. IC Role / Device Role / Timing Role: Level-shifting bidirectional serial and control signals during firmware update and calibration sequences. Use Value: Enables hot-plug-safe voltage translation without direction glitches - critical for field-service tool interoperability. | Use Scenario: Aggregating outputs from multiple 3.3 V image sensors into a 1.8 V ASIC processing pipeline. IC Role / Device Role / Timing Role: Translating parallel pixel data and frame sync strobes with matched propagation delay across all 8 channels. Use Value: Ensures <100 ps inter-channel skew, preventing pixel misalignment in real-time image stitching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bidirectional level translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TXS0108EZRGR | 8-bit auto-direction translator with 1.65 V to 5.5 V support; 5.5 V tolerant inputs; slightly higher 5.2 ns max propagation delay. | Designed for broader voltage range including 5 V microcontrollers; lacks LFCSP thermal pad. | Preferred when interfacing to 5 V legacy peripherals; requires larger QFN-20 package area. |
| SN74AVC8T245RHLR | 8-bit dual-supply translator with explicit DIR pin; 1.2 V to 3.6 V operation; 3.3 ns max delay; no auto-sensing. | Requires FPGA GPIO or dedicated logic to manage direction control; better suited for unidirectional-heavy traffic. | Select when deterministic direction control is needed or when system already dedicates pins for DIR signaling. |
Compared with TXS0108EZRGR and SN74AVC8T245RHLR, the ADG3247BCPZ uniquely combines auto-direction sensing, 3.6 V tolerance on both sides, and LFCSP thermal performance - making it optimal for compact, high-speed, mixed-voltage FPGA peripheral bridges where pin count and layout density are constrained.
Availability
ADG3247BCPZ is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, FPGA-to-ADC interface, and automotive infotainment debug port designs requiring stable component supply and long-term lifecycle assurance.
Supply support for ADG3247BCPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The ADG3247BCPZ belongs to Analog Devices' precision level translation product line, engineered specifically for reliable, low-skew, bidirectional voltage domain bridging in FPGA, ASIC, and SoC-based systems.
FAQ
What voltage ranges does the ADG3247BCPZ support on its A-side and B-side I/Os?
The ADG3247BCPZ supports 1.65 V to 3.6 V on both A-side and B-side I/Os, with independent VCCA and VCCB supplies. Inputs on either side tolerate up to 3.6 V regardless of their respective supply voltage - enabling robust interfacing between 1.8 V, 2.5 V, and 3.3 V domains without damage or clamping.
Does the ADG3247BCPZ require an external direction control signal?
No, the ADG3247BCPZ uses internal auto-direction sensing circuitry that detects data flow direction on each channel dynamically. This eliminates the need for an external DIR pin or FPGA GPIO assignment, simplifying PCB layout and reducing firmware overhead compared to manually controlled translators like the SN74AVC8T245RHLR.
What is the maximum data rate supported by the ADG3247BCPZ in a bidirectional interface?
The ADG3247BCPZ achieves a typical propagation delay of 3.5 ns at 3.3 V, supporting reliable operation up to approximately 100 MHz for parallel data transfers. Its matched channel delays and sub-100 ps skew ensure timing-critical applications - such as FPGA-to-ADC handshaking or real-time sensor hub aggregation - maintain signal integrity without added setup/hold margin penalties.
Can the ADG3247BCPZ be used with 5 V peripherals?
No - the ADG3247BCPZ inputs are rated for 3.6 V maximum, and exceeding this risks permanent damage. For 5 V peripheral interfacing, consider the TXS0108EZRGR, which offers 5.5 V input tolerance. The ADG3247BCPZ is strictly intended for 1.65 V to 3.6 V domain bridging, such as 1.8 V ↔ 3.3 V or 2.5 V ↔ 3.3 V connections.
Is the exposed thermal pad on the ADG3247BCPZ package required to be soldered to ground?
Yes - the exposed thermal pad on the ADG3247BCPZ LFCSP package must be soldered to a solid GND plane for optimal thermal performance, EMI suppression, and signal integrity. Analog Devices' recommended land pattern specifies a 3×3 array of thermal vias connecting the pad directly to inner-layer ground planes, and omitting this compromises both reliability and high-speed timing behavior of the ADG3247BCPZ.
ADG3247BCPZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad, CSP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Type:
- Bus Switch
- Circuit:
- 8 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.5V, 3.3V
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-LFCSP (6x6)
ADG3247BCPZ FAQ
1.How can I place an order for ADG3247BCPZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ADG3247BCPZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADG3247BCPZ reliable?
The price and inventory of ADG3247BCPZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADG3247BCPZ is usually 5 days.
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ADG3247BCPZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADG3247BCPZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADG3247BCPZ?
For technical support, including ADG3247BCPZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADG3247BCPZ requirements.
6.How does Aetrix verify that ADG3247BCPZ is sourced from the original manufacturer or authorized distributors?
All ADG3247BCPZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADG3247BCPZ meets industry standards.
7.What is the process for return or replacement of ADG3247BCPZ?
All ADG3247BCPZ units undergo pre-shipment inspection (PSI). If there is an issue with ADG3247BCPZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADG3247BCPZ part is unused and in its original packaging.
Return procedure for ADG3247BCPZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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