Analog Devices Inc. ADL5369ACPZ-R7

Overview

ADL5369ACPZ-R7 from Analog Devices is a 300 MHz to 1100 MHz balanced passive mixer with integrated RF balun, dual LO switch, and IF amplifier. It delivers 6.2 dB power conversion loss, 7.2 dB SSB noise figure, and +28 dBm input IP3 at 5 V supply, enabling high-linearity downconversion in cellular base station receivers and transmit observation paths.

For engineers reviewing the ADL5369ACPZ-R7 datasheet, ADL5369ACPZ-R7 pinout, ADL5369ACPZ-R7 application, or ADL5369ACPZ-R7 equivalent, key selection criteria include RF/LO frequency coverage (300–1100 MHz / 330–1550 MHz), dual-LO switching capability (<40 ns), power-down functionality (<200 μA), and 5 mm × 5 mm 20-lead LFCSP package compatibility with high-density RF layouts.

Technical Context

The ADL5369ACPZ-R7 integrates a doubly balanced passive MOSFET mixer core with on-die RF balun and SPDT LO switch - enabling single-ended 50 Ω RF/LO interface while maintaining >−25 dBm LO-to-RF leakage and −42 dBc RF-to-IF isolation. Its BiCMOS process supports operation from 3.3 V to 5 V with externally programmable bias via R9.

Two independent LO inputs (LOI1/LOI2) are routed through a high-isolation FET switch controlled by LOSW, allowing rapid TDD-mode oscillator switching. Mixer gate bias (VGS0/VGS1) sets linearity/noise trade-offs, and PWDN enables <200 μA standby current only under ≤3.6 V supply per datasheet specification.

Key Specifications

Pinout & Package

ADL5369ACPZ-R7 uses a 5 mm × 5 mm, 20-lead LFCSP package with exposed thermal pad soldered to ground. Pin numbering follows top-view orientation per Figure 2 of Rev. A datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar balanced mixer applications.

Compared with ADL5369ACPZ-R7, ADL5367ACPZ-R7 trades RF bandwidth extension for reduced linearity and missing IF gain, while ADL5365ACPZ-R7 prioritizes ultra-high IIP3 at the expense of dual-LO flexibility and sub-1 GHz coverage - making ADL5369ACPZ-R7 uniquely balanced for cellular infrastructure with TDD agility requirements.

Availability

ADL5369ACPZ-R7 is available at Aetrix Electronics and suitable for cellular base station receivers, transmit observation receivers, and radiolink downconverters requiring stable component supply, long-term lifecycle support, and traceable sourcing for telecom infrastructure programs.

Supply support for ADL5369ACPZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving communications, industrial, and instrumentation markets since 1965.

The ADL5369ACPZ-R7 belongs to Analog Devices' high-linearity RF mixer product line, designed specifically for wireless infrastructure applications demanding wideband operation, dual-LO agility, and thermal stability in base station and test equipment front-ends.

FAQ

What is the recommended LO drive level for optimal performance of the ADL5369ACPZ-R7?

The ADL5369ACPZ-R7 achieves best dynamic performance at 0 dBm LO input power, delivering 6.2 dB conversion loss and +28 dBm IIP3. LO drive can range from −6 dBm to +10 dBm; however, below −3 dBm increases conversion loss by up to 1.2 dB, and above +5 dBm yields diminishing IIP3 returns while increasing DC current draw. Always maintain 50 Ω termination at LOI1/LOI2 regardless of selection state.

Can the ADL5369ACPZ-R7 operate with a 3.3 V supply, and how does performance change?

Yes, the ADL5369ACPZ-R7 supports 3.3 V operation with adjusted resistor R9 (226 Ω). At 3.3 V, typical conversion loss increases to 6.5 dB, SSB noise figure rises to 7.4 dB, and IIP3 decreases to +24 dBm. Quiescent current drops to 55 mA, and power-down current falls to 150 μA. The PWDN function is only guaranteed functional at VS ≤ 3.6 V per datasheet Section 2.

How is the dual-LO switching controlled on the ADL5369ACPZ-R7, and what is the switching speed?

Dual-LO switching on the ADL5369ACPZ-R7 is controlled by the LOSW pin: 0 V selects LOI1, and 3 V selects LOI2. The internal SPDT FET switch achieves <40 ns switching time with >40 dB isolation between ports across the full RF band. VPSW must be supplied at the same voltage as VLO2/VLO3 to ensure consistent timing and threshold behavior.

What is the purpose of the VGS0 and VGS1 pins on the ADL5369ACPZ-R7, and how do they affect performance?

VGS0 and VGS1 are 3 V logic-controlled mixer gate bias inputs that adjust the trade-off between linearity and noise. Grounding both yields nominal +28 dBm IIP3 and 7.2 dB noise figure. Setting combinations (0/1, 1/0, 1/1) shifts IIP3 by ±2 dB and noise figure by ±0.3 dB - enabling real-time adaptation in dynamic RF environments without changing external components. The ADL5369ACPZ-R7 datasheet provides exact curves in Figures 34–36.

Is an evaluation board available for the ADL5369ACPZ-R7, and what does it support?

Yes, the ADL5369-EVALZ evaluation board is available from Analog Devices. It supports full characterization of the ADL5369ACPZ-R7 at both 3.3 V and 5 V supply, including RF/LO/IF port matching networks, SMA connectors, and jumpers for VGS0/VGS1 and LOSW configuration. The board implements the JEDEC-standard thermal layout used to measure θJB = 14.74°C/W, enabling accurate thermal modeling in customer designs.