Analog Devices Inc. ADM1051JR-REEL7
- Part No.:
- ADM1051JR-REEL7
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- -
- Datasheet:
-
ADM1051JR-REEL7.pdf
- Description:
- IC REG CTRLR BUCK 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,464
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADM1051JR-REEL7 from Analog Devices is a dual-channel precision voltage regulator controller for PC motherboard AGP/ICH power rail generation and active bus termination. It delivers fixed 1.515 V (Channel 1) and 1.818 V (Channel 2) outputs with ±2.5% accuracy over line, load, and temperature (0°C to 70°C), drives external N-channel MOSFETs in source-follower configuration, and features hiccup-mode fault protection and multilevel SHDN1 voltage-selectable operation (1.5 V / 3.3 V modes).
For engineers reviewing the ADM1051JR-REEL7 datasheet, ADM1051JR-REEL7 pinout, ADM1051JR-REEL7 application, or ADM1051JR-REEL7 equivalent, this page provides verified technical context, exact pin functions, real-world sequencing behavior, hiccup-mode timing parameters, and validated alternatives for desktop/server power management design.
Technical Context
The ADM1051JR-REEL7 integrates two independent control amplifiers with a shared 1.2 V bandgap reference, each driving external N-channel MOSFETs as source-followers. Channel 1 supports four SHDN1 voltage-defined modes (shutdown, 1.5 V, 3.3 V pass-through, and default 1.5 V), while Channel 2 operates at fixed 1.818 V with dedicated active-low SHDN2 control.
Hiccup-mode protection triggers when output falls below 0.8 × VOUT, enforcing 1:40 duty-cycle pulsing (on-time 0.5–1.5 ms, off-time 20–60 ms, hold-off 30–90 ms). Power-on reset activates above 6–9 V VCC, disabling outputs until threshold is met-except Channel 2 of ADM1051A variant, which is not applicable here since ADM1051JR-REEL7 is the base ADM1051 version.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage (Ch1) | 1.515 V nominal; selectable to 3.3 V via SHDN1 voltage level (4.3–5.3 V); enables AGP TYPEDET-compatible mode switching |
| Output Voltage (Ch2) | 1.818 V fixed; optimized for ICH rail generation with no voltage-select capability |
| Accuracy | ±2.5% over line (VIN = 3.0–3.6 V), load (10 mA–1 A), and temperature (0°C–70°C); ensures stable core/bus termination |
| Control Amplifier Slew Rate | 3 V/µs; enables fast transient response during 10 mA ↔ 2 A load steps without external compensation |
| Hiccup Mode Threshold | 0.8 × VOUT; detects output collapse due to short-circuit and initiates pulsed gate drive to limit MOSFET power dissipation |
| Supply Current (Active) | 2.4–4.0 mA at VCC = 12 V; low quiescent draw suitable for always-on motherboard standby domains |
| Shutdown Current | 600–1000 µA with both channels disabled; minimizes leakage in powered-down states |
Pinout & Package
ADM1051JR-REEL7 is housed in an 8-lead narrow-body SOIC (R-8) package with θJA = 150°C/W, rated for 0°C to 70°C commercial operation. Pin 1 is FORCE 2; pin 8 is VCC. All pins are electrically defined per Analog Devices' official pin function table.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FORCE 2 (Pin 1) | Channel 2 control amplifier output | Drives gate of external N-channel MOSFET; high-swing (10 V) and low-swing (2 V) capability ensures full turn-on/turn-off |
| SENSE 2 (Pin 2) | Channel 2 feedback input | Connects to MOSFET source node; high impedance (50 kΩ) minimizes loading on resistor-divider network |
| SHDN2 (Pin 3) | Channel 2 shutdown enable | Active-low digital input with 50 µA internal pull-up; forces FORCE 2 low when asserted |
| GND (Pin 4) | Device ground reference | Common return for all internal circuitry; must be routed separately from high-current load paths per layout guidelines |
| SHDN1 (Pin 5) | Channel 1 multilevel control input | Four-mode interface: <0.8 V (shutdown), 2–3.9 V (1.5 V), 4.3–5.3 V (3.3 V pass-through), >6.2 V/floating (1.5 V default) |
| SENSE 1 (Pin 6) | Channel 1 feedback input | Connects to Channel 1 MOSFET source; identical 50 kΩ impedance to SENSE 2 for matched loop stability |
| FORCE 1 (Pin 7) | Channel 1 control amplifier output | Optimized for high-capacitance MOSFETs (e.g., PHD55N03LT); supports fast gate charging/discharging for <5 µs settling |
| VCC (Pin 8) | Main supply input | 12 V nominal (abs max 14 V); powers internal bandgap, amplifiers, and logic; POR threshold 6–9 V |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent controllers | Enables simultaneous 1.515 V AGP and 1.818 V ICH rail generation on single die, reducing BOM count and PCB area |
| No external setting resistors | Fixed output voltages set internally; eliminates resistor tolerance drift and layout sensitivity in feedback networks |
| Hiccup-mode fault protection | Self-resetting 1:40 duty-cycle pulsing prevents thermal runaway during output shorts without current-sense resistors |
| TYPEDET-compatible SHDN1 | Direct interface to PC motherboard TYPEDET signal via simple resistor divider, enabling automatic AGP 2×/4× mode selection |
| N-channel MOSFET support | Leverages lower-cost, higher-performance N-MOS devices in source-follower topology-no P-channel gate-drive complexity |
Applications
| AGP Graphics Power Management | ICH Core Rail Generation |
|---|---|
|
Use Scenario: Regulating AGP slot termination voltage on desktop/server motherboards supporting both 2× and 4× AGP modes. IC Role / Device Role / Timing Role: Dual-channel controller providing 1.515 V (4× mode) or 3.3 V (2× mode) via SHDN1 voltage selection, synchronized with TYPEDET signal timing. Use Value: Eliminates need for separate regulators or manual jumpers; ensures correct termination voltage per AGP specification without firmware intervention. |
Use Scenario: Generating stable 1.818 V supply for Intel I/O Control Hub (ICH) chipsets requiring tight regulation and sequencing. IC Role / Device Role / Timing Role: Channel 2 acts as dedicated ICH rail controller with fixed 1.818 V output, independent shutdown (SHDN2), and hiccup-mode protection. Use Value: Meets ICH voltage tolerance requirements (±2.5%) across temperature and load, preventing chipset malfunction or data corruption. |
| Active Bus Termination | Desktop Motherboard Power Sequencing |
|
Use Scenario: Providing precision termination voltage for high-speed parallel buses (e.g., AGP, PCI-X) to minimize signal reflections and EMI. IC Role / Device Role / Timing Role: Delivers low-noise, low-drift 1.515 V/1.818 V rails directly to termination resistors; closed-loop settling time <5 µs maintains signal integrity during transients. Use Value: Reduces bit-error rate by stabilizing bus DC levels; hiccup-mode prevents catastrophic failure during bus short events. |
Use Scenario: Coordinating power-up sequence between AGP and ICH rails on legacy desktop platforms where sequencing margins are critical. IC Role / Device Role / Timing Role: Channel 1 (1.515 V) and Channel 2 (1.818 V) start simultaneously after VCC POR threshold (6–9 V), ensuring monotonic ramp without reverse bias. Use Value: Avoids latch-up or undefined state in companion logic chips by guaranteeing both rails rise within safe voltage differentials. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel voltage regulator controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADM1051AAR-REEL7 | Includes ICH-sequencing enhancements: Channel 2 has 5 VSB-powered startup to prevent >2 V drop vs. 3.3 V rail; hiccup mode disabled on Ch2 | Required for newer ICH chipsets with strict sequencing mandates; not backward-compatible for pure AGP-only designs | Select ADM1051AAR-REEL7 only if platform requires guaranteed 1.818 V rail tracking to 3.3 V supply during power-up |
| TPS51100PWR | Single-channel 1.5 V/1.8 V dual-output controller with integrated MOSFET drivers; no SHDN1 voltage-select mode; ±1.5% accuracy | Targets DDR memory termination; lacks TYPEDET compatibility and hiccup-mode fault recovery; uses different feedback architecture | Choose TPS51100PWR for cost-sensitive DDR VTT applications where AGP mode-switching is unnecessary |
Compared with ADM1051JR-REEL7, ADM1051AAR-REEL7 adds sequencing safety for modern ICH but removes hiccup protection on Channel 2, while TPS51100PWR simplifies design for DDR termination but cannot replace AGP TYPEDET functionality or deliver the same fault resilience.
Availability
ADM1051JR-REEL7 is available at Aetrix Electronics and suitable for desktop computers, servers, and workstations requiring stable component supply, precise dual-rail generation, and robust hiccup-mode fault handling in high-noise motherboard environments.
Supply support for ADM1051JR-REEL7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and computing markets with precision power, sensing, and interface solutions.
The ADM1051 family was designed specifically for PC motherboard power management-delivering dual-rail AGP/ICH regulation, TYPEDET compatibility, and hiccup-mode protection without external resistors or complex layout constraints.
FAQ
What is the key functional difference between ADM1051JR-REEL7 and ADM1051AAR-REEL7?
The ADM1051JR-REEL7 is the base version with full hiccup-mode protection on both channels and standard power-on reset behavior. ADM1051JR-REEL7's Channel 2 enters hiccup mode if output drops below 0.8 × 1.818 V. In contrast, ADM1051AAR-REEL7 disables hiccup mode on Channel 2 and implements 5 VSB-assisted startup to ensure Channel 2 never falls more than 2 V below the 3.3 V rail-critical for newer ICH chipsets. ADM1051JR-REEL7 remains optimal for legacy AGP-focused designs.
How does ADM1051JR-REEL7 implement AGP TYPEDET compatibility without external logic?
ADM1051JR-REEL7 uses its SHDN1 pin as a multilevel analog input: applying 0 V shuts down Channel 1, 2–3.9 V selects 1.515 V output (4× AGP), 4.3–5.3 V forces 3.3 V pass-through (2× AGP), and floating or >6.2 V defaults to 1.515 V. This matches TYPEDET signaling directly-no FPGA, microcontroller, or level-shifter required. The ADM1051JR-REEL7 datasheet confirms this behavior in Table I and Figure 2.
What external components are mandatory for ADM1051JR-REEL7 operation?
ADM1051JR-REEL7 requires two external N-channel MOSFETs (e.g., PHD55N03LT for Channel 1, MTD3055VL for Channel 2), decoupling capacitors (≥100 µF at each MOSFET drain/source, ≥1 µF at VCC), and feedback resistors only if custom output voltages are needed-though the ADM1051JR-REEL7 is factory-configured for 1.515 V/1.818 V, so resistors are optional. No external current-sense or voltage-setting resistors are needed for nominal operation.
Does ADM1051JR-REEL7 support power sequencing between its two channels?
No-ADM1051JR-REEL7 does not provide programmable inter-channel sequencing. Both channels enable simultaneously after VCC crosses the 6–9 V power-on reset threshold. For strict sequencing (e.g., ensuring Channel 2 rises before Channel 1), external circuitry like RC delays on SHDN1/SHDN2 is required. The ADM1051A variant (ADM1051AAR-REEL7) adds partial sequencing via 5 VSB biasing, but that is not part of the ADM1051JR-REEL7 feature set.
What is the maximum load current ADM1051JR-REEL7 can regulate stably?
ADM1051JR-REEL7 is characterized for stable operation up to 2 A per channel, as confirmed by closed-loop settling time (5 µs), load regulation (±5 mV), and typical performance curves (TPC 4–5). Stability assumes proper PCB layout (separate sense/ground paths), low-ESR decoupling (≤50 mΩ), and recommended MOSFETs (e.g., PHD55N03LT, MTD3055VL). Exceeding 2 A risks thermal overload of the external MOSFET-not the ADM1051JR-REEL7 itself-as the IC only drives the gate.
ADM1051JR-REEL7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Type:
- -
- Function:
- -
- Output Configuration:
- -
- Topology:
- -
- Number of Outputs:
- -
- Output Phases:
- -
- Voltage - Supply (Vcc/Vdd):
- -
- Frequency - Switching:
- -
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- -
- Clock Sync:
- -
- Serial Interfaces:
- -
- Control Features:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
ADM1051JR-REEL7 FAQ
1.How can I place an order for ADM1051JR-REEL7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADM1051JR-REEL7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADM1051JR-REEL7 reliable?
The price and inventory of ADM1051JR-REEL7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADM1051JR-REEL7 is usually 5 days.
3.What payment methods are accepted for ADM1051JR-REEL7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADM1051JR-REEL7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADM1051JR-REEL7?
ADM1051JR-REEL7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADM1051JR-REEL7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADM1051JR-REEL7?
For technical support, including ADM1051JR-REEL7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADM1051JR-REEL7 requirements.
6.How does Aetrix verify that ADM1051JR-REEL7 is sourced from the original manufacturer or authorized distributors?
All ADM1051JR-REEL7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADM1051JR-REEL7 meets industry standards.
7.What is the process for return or replacement of ADM1051JR-REEL7?
All ADM1051JR-REEL7 units undergo pre-shipment inspection (PSI). If there is an issue with ADM1051JR-REEL7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADM1051JR-REEL7 part is unused and in its original packaging.
Return procedure for ADM1051JR-REEL7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADM1051JR-REEL7 Tags

-
UCC28C45DR
Texas Instruments

-
UCC28C40DR
Texas Instruments

-
UCC28C43DR
Texas Instruments

-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments

-
MIC2102YML-TR
Microchip Technology

-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments

-
LM5155DSSR
Texas Instruments

-
LM25085MYX/NOPB
Texas Instruments

-
UCC2813DTR-0
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
