Analog Devices Inc. ADM1065ASUZ

Overview

ADM1065ASUZ from Analog Devices is a configurable supervisory and sequencing IC for multivoltage systems, featuring 10 programmable supply fault detectors with ±1% accuracy across −40°C to +85°C, 10 SMBus-programmable driver outputs (6 charge-pumped up to 14 V for N-FET gate drive), and a state-machine-based sequencing engine supporting up to 63 states. It enables precise power-up/down sequencing and fault handling in DSP/FPGA supply rails.

For engineers reviewing the ADM1065ASUZ datasheet, ADM1065ASUZ pinout, ADM1065ASUZ application, or ADM1065ASUZ equivalent, this page delivers verified technical context, real-world design meaning of key specs, validated pin functions, and two confirmed alternative parts for multivoltage board-level power management.

Technical Context

The ADM1065ASUZ implements a deterministic state-machine sequencing engine that triggers output transitions based on input events-undervoltage, overvoltage, or out-of-window faults-with programmable hysteresis (up to 1.02 V) and digital glitch filtering (0–100 µs). Its dual-mode inputs (VX1–VX5) serve either as high-impedance analog comparators (0.573–1.375 V range) or CMOS/TTL logic inputs.

Power is autonomously arbitrated from the highest active supply among VH (up to 14.4 V) or VP1–VP4 (up to 6.0 V), regulating VDDCAP to 4.75 V via internal LDOs; no external regulator is needed. Six PDOs (PDO1–PDO6) integrate charge-pump circuitry enabling 12.5 V typical gate drive at 20 µA average current, while PDO7–PDO10 operate as LV logic drivers with pull-up to VDDCAP or VPx.

Key Specifications

Pinout & Package

ADM1065ASUZ is packaged in a 40-lead, 6 mm × 6 mm LFCSP with exposed pad (NC, soldered for mechanical stability). All ground pins (GND, AGND, REFGND, PDOGND) must be connected together in layout. VDDCAP requires a mandatory 10 µF decoupling capacitor to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multivoltage supervisory and sequencing applications.

Compared with ADM1066ASUZ, ADM1065ASUZ lacks the dedicated watchdog but matches all sequencing, supervision, and HV drive capabilities-making it optimal for cost-sensitive, non-safety-critical multivoltage boards. Against TPS659122ZQWR, ADM1065ASUZ provides greater flexibility in rail count, voltage range, and external FET control, at the expense of integrated regulation.

Availability

ADM1065ASUZ is available at Aetrix Electronics and suitable for server/routers, DSP/FPGA supply sequencing, central office systems, multivoltage line cards, and in-circuit supply margining requiring stable component supply and long-term lifecycle support.

Supply support for ADM1065ASUZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, communications, automotive, and healthcare markets since 1965.

The ADM1065ASUZ belongs to Analog Devices' Super Sequencer® family-designed specifically for deterministic, software-configurable power sequencing and fault monitoring in complex multivoltage systems such as servers, telecom infrastructure, and high-end FPGA platforms.

FAQ

What is the maximum supply voltage that ADM1065ASUZ can monitor on the VH pin?

The ADM1065ASUZ supports a high-range input of 6.0 V to 14.4 V on the VH pin, enabling direct supervision of 12 V backplane supplies without external resistive dividers. Absolute maximum rating is 16 V, but operation above 14.4 V violates specification limits and risks incorrect fault detection. The VH pin also serves as a primary power source for the device when active.

How does ADM1065ASUZ handle power arbitration when multiple supplies are active?

ADM1065ASUZ uses an internal VDD arbitrator that selects the highest valid supply among VH and VP1–VP4 (all ≥3.0 V) to regulate VDDCAP to 4.75 V. If two supplies differ by <100 mV, the one that first asserts control retains it-even if another rises slightly later. This architecture ensures robust operation during hot-swap or brownout events without external OR-ing circuitry.

Can ADM1065ASUZ drive N-channel MOSFETs directly, and which pins support this?

Yes-ADM1065ASUZ drives N-FET gates directly using its charge-pumped outputs PDO1 through PDO6, delivering up to 14 V at 20 µA average current. These pins generate internally boosted voltage from VCCP (5.25 V) and require only a 10 µF reservoir capacitor on VCCP. PDO7–PDO10 lack charge-pump capability and are limited to logic-level drive.

What is the role of the VX1–VX5 pins in ADM1065ASUZ, and how are they configured?

VX1–VX5 are dual-function pins configurable either as high-impedance analog comparators (0.573–1.375 V threshold range, 3.14 mV resolution) or as CMOS/TTL digital inputs (VIH ≥ 2.0 V, VIL ≤ 0.8 V). Configuration is done via EEPROM registers; a pin cannot serve both roles simultaneously. This flexibility allows reuse of unused analog inputs as status flags or control signals without additional GPIOs.

Does ADM1065ASUZ require external components for basic operation, and which ones are mandatory?

Yes-ADM1065ASUZ requires three mandatory external components: a 10 µF capacitor between VDDCAP and GND for supply decoupling/reservoir function, a 10 µF capacitor between VCCP and GND for charge-pump stability, and pull-up resistors on SDA/SCL for SMBus communication. No external resistors are needed for VH/VPx/VXx inputs due to integrated attenuators and high-Z design.