Analog Devices Inc. ADM1066ASU

Overview

ADM1066ASU from Analog Devices is a configurable supervisory and sequencing IC for multivoltage systems, integrating 10 supply fault detectors (±1% accuracy), a 12-bit SAR ADC, six 8-bit DACs (0.300 V–1.551 V output), and a state-machine-based sequencing engine supporting up to 63 states. It enables closed-loop voltage margining and in-circuit testing of DSP/FPGA power rails.

For engineers reviewing the ADM1066ASU datasheet, ADM1066ASU pinout, ADM1066ASU application, or ADM1066ASU equivalent, key selection criteria include its dual-mode programmable driver outputs (charge-pumped HV mode for N-FET gate drive; LV push/pull/open-collector), SMBus-configurable sequencing logic, 0.573 V–14.4 V input supervision range, and on-chip EEPROM for persistent configuration storage.

Technical Context

The ADM1066ASU implements a deterministic state-machine sequencing engine with conditional transitions triggered by input events (e.g., supply OK, fault, timer expiry), enabling precise power-up/down control and fault-handling workflows across up to 10 voltage rails. Its arbitration circuit selects VDDCAP from the highest active VPx or VH rail (≥3.0 V), ensuring operational redundancy.

Supervision uses selectable input attenuators (VH: high/mid-range; VPx: mid/low/ultralow; VXx: ultralow only) to support thresholds from 0.573 V to 14.4 V with ±0.05% attenuation error. The 12-bit ADC digitizes all supervised voltages and two auxiliary inputs using a 2.048 V reference, while six buffered DACs provide trim/feedback node adjustment for dc-dc converters.

Key Specifications

Pinout & Package

ADM1066ASU is available in a 40-lead, 6 mm × 6 mm LFCSP package with exposed pad (NC, for mechanical stability only). Pin functions are validated per Analog Devices' Rev. F datasheet Figures 3 and Table 4.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory and sequencing applications.

Compared with ADM1166ACPZ and TPS40400RHLR, the ADM1066ASU uniquely combines 10-supply supervision, six DACs, two auxiliary ADC inputs, and a 63-state sequencing engine in a single chip-making it the only option for high-complexity, closed-loop margining applications in telecom and high-end computing where both precision and configurability are non-negotiable.

Availability

ADM1066ASU is available at Aetrix Electronics and suitable for central office systems, servers/routers, and DSP/FPGA supply sequencing requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for ADM1066ASU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADM1066ASU belongs to Analog Devices' Super Sequencer® family, designed specifically for intelligent power management in multivoltage systems requiring precision supervision, dynamic margining, and deterministic sequencing-targeting telecom infrastructure, enterprise computing, and high-reliability embedded platforms.

FAQ

What is the maximum number of voltage rails the ADM1066ASU can supervise and sequence?

The ADM1066ASU supports supervision and sequencing of up to 10 independent voltage rails using its VH, VP1–VP4, and VX1–VX5 inputs. All 10 rails can be monitored for undervoltage, overvoltage, or out-of-window faults with ±1% accuracy across temperature, and their power-up/power-down order and timing are fully controlled by the 63-state sequencing engine. This capability is explicitly confirmed in the General Description and Specifications sections of the ADM1066 datasheet Rev. F.

Does the ADM1066ASU support closed-loop voltage margining, and how is it implemented?

Yes, the ADM1066ASU implements a complete closed-loop margining system using its integrated 12-bit ADC and six 8-bit DACs. The ADC reads back actual rail voltages (including VH, VPx, and VXx inputs), and the DACs inject precise adjustments into the feedback or trim nodes of dc-dc converters. This loop enables dynamic, real-time voltage offset control-verified in-circuit during production test or used for runtime optimization. The architecture is detailed in the "Closed-Loop Supply Margining" section (page 23) of the ADM1066 datasheet Rev. F.

What are the key differences between the HV and LV modes of the ADM1066ASU's programmable driver outputs?

PDO1–PDO6 support two distinct output modes: HV mode uses an internal charge pump to deliver up to 14 V at 7 µA for direct N-FET gate drive, while LV mode offers push-pull, open-collector, or weak pull-up configurations referenced to VDDCAP or VPx. PDO7–PDO10 operate LV-only. These modes are selected per-output via configuration registers and enable flexible interfacing-from driving logic enables to controlling high-side FETs-without external components. The distinction is defined in the "Outputs" section (page 18) and Table 1 of the ADM1066 datasheet Rev. F.

How does the ADM1066ASU achieve power supply redundancy, and what is the minimum operating voltage?

The ADM1066ASU achieves redundancy through supply arbitration: its internal VDDCAP regulator automatically selects power from the highest valid voltage among VH (3.0–14.4 V) or VP1–VP4 (3.0–6.0 V), with minimal dropout (~0.2 V). This ensures operation continues even if one supply fails. The minimum required supply voltage is 3.0 V on any VPx or VH pin, as specified in Table 1 (Power Supply Arbitration) and the "Powering the ADM1066" section (page 14) of the ADM1066 datasheet Rev. F.

Can the ADM1066ASU's configuration be updated in-system, and where is it stored?

Yes, the ADM1066ASU's full configuration-including sequencing states, fault thresholds, DAC settings, and GPIO behavior-is stored in 256 bytes of on-chip EEPROM and can be updated in-system via SMBus. Configuration download occurs automatically at power-up, and updates can be performed dynamically using Analog Devices' GUI-based software or custom firmware. This persistent, field-upgradable storage eliminates the need for external memory or host processor intervention, as documented in the "EEPROM" and "Configuration Download at Power-Up" sections (pages 27 and 26) of the ADM1066 datasheet Rev. F.