Analog Devices Inc. ADM1067ACP

Overview

ADM1067ACP from Analog Devices is a configurable supervisory and sequencing IC with integrated open-loop margining DACs. It monitors up to 10 voltage rails with <1.0% accuracy across temperature, implements state-machine-based power-up/down sequencing via 10 programmable driver outputs (PDOs), and provides six 8-bit DACs (0.300 V–1.551 V) for dc-dc converter trim node adjustment-used in multivoltage server line cards requiring precise supply validation.

For engineers reviewing the ADM1067ACP datasheet, ADM1067ACP pinout, ADM1067ACP application, or ADM1067ACP equivalent, key selection concerns include VH/VPx supply arbitration architecture, dual-mode PDO drive capability (charge-pumped HV gate drive or LV logic-level output), VXx dual-function input configuration, DAC output settling time (2 μs into 50 pF), and EEPROM-based sequencing engine programming via SMBus.

Technical Context

The ADM1067ACP integrates a 63-state sequencing engine (SE) that executes conditional state transitions based on input events-including undervoltage, overvoltage, and out-of-window faults detected by 10 SFD inputs-and supports fault-triggered interrupt generation and watchdog integration. Its SE operates from an internal 90–110 kHz oscillator, enabling microsecond-scale state change timing (10 μs).

Power is derived from the highest active rail among VH (up to 14.4 V) or VP1–VP4 (up to 6.0 V), regulated to VDDCAP (2.7–5.4 V) via an on-chip arbitration circuit with ~0.2 V dropout. Six PDOs (PDO1–PDO6) support charge-pumped high-voltage drive (up to 14 V) for N-FET gate control, while all 10 PDOs offer configurable pull-up modes (to VDDCAP or VPx) and push-pull operation.

Key Specifications

Pinout & Package

ADM1067ACP is packaged in a 40-lead, 6 mm × 6 mm LFCSP with exposed pad (NC). Pin functions are validated per Analog Devices Rev. E datasheet Figures 3 and Table 4.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory and sequencing applications.

Compared with ADM1067ACP, ADM1066ACP removes DAC functionality while retaining identical sequencing and supervision capability-making it a lower-cost alternative when margining is not required. The TPS3851G18EVM-699 is strictly a supervisor evaluation platform with no sequencing or DAC features, limiting its use to basic reset assertion rather than full-system power management.

Availability

ADM1067ACP is available at Aetrix Electronics and suitable for server power sequencing, DSP/FPGA multirail startup, and in-circuit supply margining test applications requiring stable component supply and long-term lifecycle support.

Supply support for ADM1067ACP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADM1067ACP belongs to Analog Devices' Super Sequencer® family-designed specifically for intelligent, autonomous power management in multivoltage systems such as telecom infrastructure, enterprise servers, and high-end computing platforms.

FAQ

What is the primary function of the ADM1067ACP in a power management system?

The ADM1067ACP serves as a fully integrated supervisory and sequencing controller with embedded open-loop margining capability. It monitors up to 10 voltage rails with ±1.0% accuracy, executes programmable power-up/down sequences via its 63-state sequencing engine, and adjusts six dc-dc converter outputs using its six 8-bit DACs-all within a single chip. This eliminates the need for discrete supervisors, sequencers, and external DACs in complex multivoltage designs like server line cards.

How does the ADM1067ACP handle power supply redundancy and brownout conditions?

The ADM1067ACP uses an internal VDD arbitration circuit that selects the highest active voltage among VH (up to 14.4 V) or VP1–VP4 (up to 6.0 V) to generate its internal VDDCAP supply. During brownouts, the VDDCAP decoupling capacitor (10 μF recommended) acts as a reservoir, sustaining device operation until the next highest supply takes over. This architecture ensures uninterrupted sequencing and supervision even during transient supply dips or hot-swap events.

Can the ADM1067ACP drive N-channel MOSFETs directly, and if so, which pins support this?

Yes-the ADM1067ACP can directly drive N-channel MOSFET gates using its charge-pumped high-voltage mode on PDO1 through PDO6. These outputs deliver up to 14 V (at 1 μA load) with internal charge pump circuitry, eliminating the need for external level shifters. PDO7–PDO10 operate only in low-voltage logic-level modes and are not suitable for direct FET gate drive.

What is the role of the MUP and MDN pins on the ADM1067ACP?

The MUP (Margin Up) and MDN (Margin Down) pins are dedicated hardware control inputs that force all six DACs to their minimum or maximum output codes, respectively. When asserted, MUP lowers DAC output voltage to induce a corresponding increase in dc-dc output (margining up), while MDN raises DAC output to reduce dc-dc output (margining down). This enables rapid, pin-controlled margining during production test without SMBus communication.

Does the ADM1067ACP require external components to implement open-loop supply margining?

No-the ADM1067ACP implements open-loop margining with minimal external components: only the DAC output must be connected to the feedback node of a compatible dc-dc converter (typically via a resistor divider). No external DACs, op-amps, or precision references are needed. The device's internal 2.048 V reference, 8-bit DACs, and buffered outputs provide full margining functionality within the IC itself.