Analog Devices Inc. ADM1067ACPZ

Overview

ADM1067ACPZ from Analog Devices is a configurable supervisory and sequencing IC with integrated open-loop margining DACs, supporting up to 10 supply supervision channels (<1.0% accuracy across temperature), 10 programmable driver outputs (PDOs), six 8-bit voltage-output DACs (0.300 V–1.551 V), SMBus interface, and a state-machine-based sequencing engine for complex power-up/down control in multivoltage systems such as DSP/FPGA boards.

For engineers reviewing the ADM1067ACPZ datasheet, ADM1067ACPZ pinout, ADM1067ACPZ application, or ADM1067ACPZ equivalent, key selection considerations include its dual-mode PDO architecture (HV charge-pump for N-FET gate drive and LV push-pull/OC modes), 0.573 V–14.4 V input supervision range with selectable attenuators, EEPROM-programmable sequencing logic, and 6-channel DAC margining capability for in-circuit supply testing.

Technical Context

The ADM1067ACPZ implements a 63-state sequencing engine that conditions output transitions on real-time input events (e.g., supply fault detection, digital inputs), enabling deterministic power-up, power-down, and fault-handling sequences. Its arbitration circuit selects VDDCAP from the highest of VH (up to 14.4 V) or VPx (up to 6.0 V), ensuring operational redundancy.

Each of the six DACs provides buffered 8-bit voltage output with ±0.75 LSB INL, 2.36 mV LSB step size, and 2 μs settling time into 50 pF; DAC outputs interface directly with dc-dc converter feedback/trim nodes for open-loop margining. Input supervision uses high-impedance comparators with programmable glitch filtering (0–100 μs) and attenuation options per channel.

Key Specifications

Pinout & Package

ADM1067ACPZ is available in a 40-lead, 6 mm × 6 mm LFCSP package with exposed pad (NC, soldered for mechanical stability). Pin functions are validated per Analog Devices Rev. E datasheet Figures 3 and Table 4.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supply supervision and sequencing applications.

Compared with ADM1066ACPZ, ADM1067ACPZ adds six DACs for margining but shares identical sequencing logic and supervision accuracy; versus TPS40400RHLR, ADM1067ACPZ offers standalone EEPROM-based operation and industry-standard SMBus, reducing host processor dependency and simplifying validation.

Availability

ADM1067ACPZ is available at Aetrix Electronics and suitable for server/routers, DSP/FPGA supply sequencing, central office systems, multivoltage line cards, and in-circuit testing requiring stable component supply and long-term lifecycle support.

Supply support for ADM1067ACPZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADM1067ACPZ belongs to Analog Devices' Super Sequencer® family, designed specifically for intelligent, configurable power management in complex multirail systems where reliability, programmability, and margining capability are critical.

FAQ

What is the primary function of the ADM1067ACPZ in a power management system?

The ADM1067ACPZ serves as a fully configurable supervisory and sequencing controller with integrated open-loop margining. It monitors up to 10 voltage rails with ±1.0% accuracy, executes programmable power-up/down sequences using a 63-state engine, and adjusts six dc-dc converter outputs via its 8-bit DACs - all without requiring external microcontroller intervention. The ADM1067ACPZ replaces discrete supervisors, timers, and margining circuits in high-reliability systems.

How does the ADM1067ACPZ achieve power supply redundancy?

The ADM1067ACPZ implements automatic VDDCAP arbitration among VH (up to 14.4 V) and VP1–VP4 (up to 6.0 V), selecting the highest valid input to power its internal LDO-regulated 4.75 V supply. This ensures continuous operation even if one supply fails or sags, and the 10 μF VDDCAP decoupling capacitor acts as a reservoir during brief brownouts. The ADM1067ACPZ does not rely on any single rail, making it ideal for mission-critical telecom and server applications.

Can the ADM1067ACPZ drive external N-channel MOSFETs directly?

Yes - the ADM1067ACPZ's PDO1 through PDO6 support an internally charge-pumped high-voltage mode capable of delivering up to 14 V at 20 μA average current, sufficient to fully enhance common N-FETs used in supply enable or OR-ing paths. This eliminates external level shifters or gate drivers. PDO7–PDO10 lack this capability and are limited to LV logic-level outputs referenced to VDDCAP or VPx. All PDO configurations are software-defined via the ADM1067ACPZ's EEPROM.

What is the role of the VX1–VX5 pins on the ADM1067ACPZ?

The VX1–VX5 pins on the ADM1067ACPZ are dual-function inputs: they operate as high-impedance (1 MΩ) supply fault detectors with ultralow threshold range (0.573 V–1.375 V) or as general-purpose digital logic inputs. Unlike VPx/VH pins, they require no external attenuators and exhibit zero attenuation error. Their flexibility allows monitoring of low-voltage rails (e.g., 1.0 V FPGA core) or serving as system reset, watchdog, or margin-control signals - all configurable via the ADM1067ACPZ's register map.

How is sequencing logic configured and updated on the ADM1067ACPZ?

Sequencing logic for the ADM1067ACPZ is stored in its 256-byte user EEPROM and loaded automatically at power-up. Configuration is performed using Analog Devices' GUI-based software, which generates binary files for SMBus upload. Runtime updates are supported via SMBus write operations to RAM-mapped sequencer registers, allowing dynamic reconfiguration without reset. The ADM1067ACPZ retains full independence - no host processor is needed for basic sequencing, though the SMBus interface enables diagnostics and field updates.