Analog Devices Inc. ADM1067ASU

Overview

ADM1067ASU from Analog Devices is a configurable supervisory and sequencing IC with integrated open-loop margining DACs for multivoltage system power management. It monitors up to 10 supplies with <1.0% accuracy across temperature, implements state-machine-based sequencing via 10 programmable driver outputs (PDOs), and provides six 8-bit voltage-output DACs (0.300 V–1.551 V) for dc-dc converter trim node adjustment. It is used in DSP/FPGA supply sequencing and in-circuit testing of margined supplies.

For engineers reviewing the ADM1067ASU datasheet, ADM1067ASU pinout, ADM1067ASU application, or ADM1067ASU equivalent, key selection considerations include its dual-mode PDO architecture (HV charge-pump for N-FET gate drive and LV push-pull/OC for logic enables), 40-lead 6 mm × 6 mm LFCSP package, SMBus programmability, and 0.573 V–14.4 V supervision range with selectable input attenuators.

Technical Context

The ADM1067ASU integrates a sequencing engine (SE) - a 63-state finite-state machine - that conditions PDO output transitions on real-time input events (e.g., supply fault detection, digital input assertion), enabling complex power-up/down sequences and fault-handling workflows. Its SE supports SMBus-programmable state jumps, watchdog integration, and interrupt generation on warnings.

Supervision is implemented via five dedicated SFD inputs (VH, VP1–VP4) with ±0.05% attenuator error and five dual-function VXx pins offering high-impedance (<1 MΩ) fault detection or general-purpose logic input capability. The six DACs are individually configurable to one of four center-voltage ranges (0.6 V, 0.8 V, 1.0 V, 1.25 V), each with ±0.75 LSB INL and 2.36 mV LSB step size.

Key Specifications

Pinout & Package

ADM1067ASU is packaged in a 40-lead, 6 mm × 6 mm lead-frame chip-scale package (LFCSP) with exposed pad (NC, soldered for mechanical stability). Power is derived from the highest of VH or VPx inputs, regulated to VDDCAP (4.75 V typical).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory and sequencing applications.

Compared with ADM1067ASU, ADM1066ASTZ removes DAC functionality but retains identical sequencing fidelity and supervision accuracy - ideal for non-margining use cases. TPS386000RGPT offers lower pin count and cost but sacrifices supervision channels, HV drive, and autonomous EEPROM-based configuration.

Availability

ADM1067ASU is available at Aetrix Electronics and suitable for server/routers, DSP/FPGA supply sequencing, and in-circuit testing of margined supplies requiring stable component supply and long-term industrial availability.

Supply support for ADM1067ASU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and control.

The ADM1067ASU belongs to Analog Devices' Super Sequencer® family, designed specifically for intelligent, autonomous power management in multivoltage computing and communications infrastructure.

FAQ

What is the primary function of the ADM1067ASU in a power management system?

The ADM1067ASU serves as an integrated supervisory and sequencing controller with open-loop margining capability. It monitors up to 10 voltage rails with ±1.0% accuracy, executes conditional power-up/down sequences using its 63-state sequencing engine, and adjusts dc-dc converter outputs via six 8-bit DACs. In systems like FPGA-based line cards, the ADM1067ASU replaces discrete supervisors, timers, and DACs - reducing design complexity while enabling in-circuit voltage margin testing without firmware changes.

How does the ADM1067ASU achieve power supply redundancy?

The ADM1067ASU achieves redundancy through its VDDCAP arbitration circuit, which automatically selects the highest valid supply among VH (up to 14.4 V) or VP1–VP4 (up to 6.0 V) to power the internal 4.75 V regulator. If one supply fails or sags, the device seamlessly switches to the next highest rail without interruption. This architecture ensures continuous operation even during brownouts - critical for telecom and server applications where uptime is essential. The ADM1067ASU's ability to derive power from multiple sources eliminates single-point-of-failure dependency.

Can the ADM1067ASU drive external N-channel MOSFETs directly?

Yes, the ADM1067ASU can directly drive external N-channel MOSFETs using PDO1–PDO6 in charge-pumped high-voltage mode. These outputs deliver up to 14 V at 1 μA, sufficient to fully enhance common logic-level N-FETs used in high-side supply switching. The internal charge pump eliminates the need for external level-shifters or gate drivers. For example, in a 12 V backplane system, PDO1 can switch an N-FET in series with a 3.3 V rail, with timing controlled by the sequencing engine. This capability is exclusive to PDO1–PDO6; PDO7–PDO10 are limited to LV logic-level signaling.

What role do the MUP and MDN pins play in ADM1067ASU operation?

The MUP (Margin Up) and MDN (Margin Down) pins provide hardware-level override of the ADM1067ASU's six DAC outputs. Asserting MUP forces all DACs to their minimum code, lowering the voltage at the dc-dc converter feedback node and causing the output to increase - effectively "marging up" the supply. Conversely, MDN forces maximum DAC codes, raising the feedback voltage and decreasing the output - "marging down." These pins enable rapid, deterministic margin testing during production without SMBus communication, and are especially valuable for in-circuit test (ICT) handlers interfacing with the ADM1067ASU on populated boards.

Is the ADM1067ASU compatible with standard SMBus protocols?

Yes, the ADM1067ASU fully complies with standard SMBus 2.0 protocols, supporting 400 kHz clock frequency, write-read operations to both volatile RAM and nonvolatile EEPROM, and standard command protocols including block write/read and process call. Its SDA and SCL pins are open-drain with internal weak pull-downs, requiring external pull-up resistors. Configuration data - including sequencing states, DAC mappings, and fault thresholds - can be downloaded at power-up from EEPROM or updated dynamically via SMBus. This compatibility ensures seamless integration with existing platform management controllers (e.g., BMCs) in server and networking equipment using the ADM1067ASU.