Analog Devices Inc. ADM1067ASUZ

Overview

ADM1067ASUZ from Analog Devices is a configurable supervisory and sequencing IC with integrated open-loop margining DACs, designed for multivoltage system power management. It monitors up to 10 supplies with <1.0% accuracy across temperature, implements state-machine-based sequencing via 10 programmable driver outputs (PDOs), and provides six 8-bit voltage-output DACs (0.300 V–1.551 V) for dc-to-dc converter trim node adjustment. Used in FPGA/DSP supply sequencing and in-circuit margin testing.

For engineers reviewing the ADM1067ASUZ datasheet, ADM1067ASUZ pinout, ADM1067ASUZ application, or ADM1067ASUZ equivalent, key selection criteria include its 40-lead LFCSP package, SMBus-controlled sequencing engine, dual-mode PDO outputs (HV charge-pump or LV push-pull), 0.573 V–14.4 V input supervision range, and EEPROM-programmable fault-handling logic.

Technical Context

The ADM1067ASUZ integrates a 63-state sequencing engine that conditions PDO output transitions on real-time input events-enabling precise power-up/down sequences, fault-triggered responses, and watchdog-integrated control. Its supervisory core uses selectable attenuators on VH and VPx inputs to support 0.573 V–14.4 V monitoring ranges with ±1% absolute accuracy.

Six buffered 8-bit DACs operate independently with 2.36 mV LSB step size, 2 μs settling time into 50 pF, and ±0.75 LSB INL. Each DAC output drives dc-to-dc feedback nodes directly, enabling open-loop margining without external op-amps or resistors-verified for −5% supply stress testing during production.

Key Specifications

Pinout & Package

ADM1067ASUZ is housed in a 40-lead, 6 mm × 6 mm LFCSP package with exposed pad (NC, soldered for mechanical stability). Power is derived from the highest of VH or VPx rails, and all ground pins (GND, AGND, REFGND, PDOGND) are internally isolated but externally tied together in typical applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory and sequencing applications.

Compared with ADM1067ASUZ, ADM1066ASUZ removes DAC functionality while retaining identical supervision and sequencing fidelity-making it a lower-cost alternative when margining is omitted. TPS659122ZQW integrates power conversion but sacrifices sequencing flexibility and DAC precision, limiting use to simpler, regulator-centric designs.

Availability

ADM1067ASUZ is available at Aetrix Electronics and suitable for FPGA/DSP supply sequencing, in-circuit margin testing, and central office line card supervision requiring stable component supply and long-term industrial lifecycle support.

Supply support for ADM1067ASUZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, communications, automotive, and aerospace markets since 1965.

The ADM1067ASUZ belongs to the Super Sequencer® family-designed specifically for multivoltage system power integrity, combining precision supervision, adaptive sequencing, and hardware-accelerated margining in single-chip solutions for high-reliability infrastructure equipment.

FAQ

What is the primary function of the ADM1067ASUZ in a power management system?

The ADM1067ASUZ serves as a configurable supervisory and sequencing controller with integrated open-loop margining DACs. It monitors up to 10 voltage rails with ±1% accuracy, executes state-machine-based power-up/down sequences using 10 programmable driver outputs, and adjusts dc-to-dc converter outputs via six 8-bit DACs. The ADM1067ASUZ replaces discrete supervisors, timers, and margining circuits in complex multivoltage systems such as FPGA boards and telecom line cards.

How does the ADM1067ASUZ achieve open-loop supply margining?

The ADM1067ASUZ implements open-loop margining using six buffered 8-bit DACs (DAC1–DAC6) that output 0.300 V–1.551 V with 2.36 mV LSB resolution. These DAC outputs connect directly to the feedback node or reference input of dc-to-dc converters, altering their regulated output voltage without closed-loop compensation. Hardware pins MUP and MDN allow immediate DAC code stepping for production test margining, and SMBus writes enable dynamic adjustment during system operation. The ADM1067ASUZ requires no external op-amps or resistor networks to perform this function.

What package options are available for the ADM1067ASUZ, and which one does this part number specify?

The ADM1067ASUZ is specified in the 40-lead, 6 mm × 6 mm LFCSP package with exposed pad (NC). This differs from the 48-lead TQFP variant (ADM1067ASTZ). The LFCSP package offers superior thermal performance (θJA = 25°C/W) and smaller PCB footprint-critical for dense server and networking applications. Pin compatibility between packages is not maintained; layout must match the ADM1067ASUZ's 40-pin LFCSP footprint, including proper grounding of GND, AGND, REFGND, and PDOGND.

Can the ADM1067ASUZ drive external N-channel MOSFETs directly, and if so, which pins support this?

Yes, the ADM1067ASUZ can directly drive external N-channel MOSFET gates using its charge-pumped high-voltage output mode on PDO1–PDO6. In this mode, each of these six outputs delivers up to 14 V (typical 12.5 V) with 20 μA average current, sufficient to fully enhance common logic-level N-FETs used in supply path switching. PDO7–PDO10 lack charge-pump circuitry and are limited to LV logic-level outputs. The ADM1067ASUZ datasheet confirms this capability in Table 1 and Figure 2's functional block diagram.

How is configuration stored and retained on the ADM1067ASUZ after power cycling?

Configuration data-including supply fault detector thresholds, PDO output states, sequencing engine state maps, and DAC settings-is stored in a 256-byte user EEPROM integrated into the ADM1067ASUZ. This nonvolatile memory retains all programmed values across power cycles and does not require external storage. Programming is performed via SMBus using Analog Devices' SuperSequencer GUI software or custom firmware; the ADM1067ASUZ automatically loads the EEPROM configuration at power-up, ensuring consistent behavior without host initialization.