Analog Devices Inc. ADM1186-1ARQZ

Overview

ADM1186-1ARQZ from Analog Devices is a quad-channel voltage up/down sequencer and monitor with programmable timing, designed for precise power supply sequencing in multi-rail systems. It features four 0.8% accurate comparators, capacitor-programmable sequence delays (±5% accuracy at 25°C), open-drain enable outputs (OUT1–OUT4), and bidirectional FAULT/SEQ_DONE pins for cascaded fault handling. It operates from 2.7 V to 5.5 V and is used in server motherboard power management.

For engineers reviewing the ADM1186-1ARQZ datasheet, ADM1186-1ARQZ pinout, ADM1186-1ARQZ application, or ADM1186-1ARQZ equivalent, key selection criteria include up/down sequencing direction control via UP/DOWN pins, blanking time configuration via BLANK_DLY, fault propagation across cascaded devices, and compatibility with resistor-divider-based UV threshold setting for diverse rail voltages (1.2 V to 5 V).

Technical Context

The ADM1186-1ARQZ implements a deterministic finite-state machine that supports both forward (power-up) and reverse (power-down) sequencing with user-defined inter-stage delays and per-rail blanking windows. Each VINx input compares against a shared 0.6 V reference with ±0.8% worst-case accuracy, enabling UV detection across rails scaled via external resistor dividers.

Its timing architecture uses five dedicated capacitor-programmed inputs-DLY_EN_OUT1 through DLY_EN_OUT4 and BLANK_DLY-to set sequence delays and blanking intervals independently; all timing currents are internally regulated at 14 µA with 1.4 V trip thresholds, ensuring ±5% delay accuracy over temperature and supply voltage.

Key Specifications

Pinout & Package

The ADM1186-1ARQZ is housed in a 20-lead QSOP package (3.9 mm × 8.7 mm, 0.65 mm pitch). Pin functions are validated per Analog Devices Rev. B datasheet Figure 3 and Table 4.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage sequencing and monitoring applications.

Compared with ADM1186-2ARQZ, the ADM1186-1ARQZ adds bidirectional sequencing, cascade-ready FAULT/SEQ_DONE signaling, and finer-grained timing control - critical for complex, multi-stage power architectures. Versus TPS659122ZQV, ADM1186-1ARQZ offers superior timing programmability and regulator agnosticism at the cost of requiring external DC/DCs.

Availability

ADM1186-1ARQZ is available at Aetrix Electronics and suitable for server motherboard design, telecom line card development, and industrial PLC controller production requiring stable component supply and long-term lifecycle support.

Supply support for ADM1186-1ARQZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.

The ADM1186 product line delivers precision power sequencing and monitoring ICs targeting complex multi-rail systems where reliability, timing accuracy, and fault containment are critical - especially in data center and infrastructure equipment.

FAQ

What is the function of the BLANK_DLY pin on the ADM1186-1ARQZ?

The BLANK_DLY pin on the ADM1186-1ARQZ accepts an external capacitor to set a uniform blanking time window applied to all VIN1–VIN4 inputs. This delay allows monitored rails sufficient time to rise above their undervoltage threshold before fault detection begins - preventing false trips during slow-ramp conditions. The blanking time accuracy is ±5% at 25°C, and the pin uses a 14 µA internal charge current with a 1.4 V trip threshold.

How does the ADM1186-1ARQZ handle fault conditions during sequencing?

When a fault occurs - such as any VINx dropping below its UV threshold or an invalid edge on UP/DOWN - the ADM1186-1ARQZ immediately disables all OUT1–OUT4 outputs, pulls SEQ_DONE low, and drives the FAULT pin low. If other ADM1186-1ARQZ devices are connected to the same FAULT net, they enter fault-handling mode synchronously. After fault hold time (35–54 µs), the device enters CLEAR FAULT state and waits for valid UP assertion to restart sequencing.

Can the ADM1186-1ARQZ be used for power-down sequencing only?

Yes, the ADM1186-1ARQZ supports standalone power-down sequencing. When in the POWER-UP DONE state, a falling edge on the DOWN pin initiates reverse-order disable of OUT4 through OUT1, using the same DLY_EN_OUTx capacitor-programmed delays as in power-up - though no blanking time is applied during power-down. All outputs are turned off, SEQ_DONE is deasserted, and the device returns to WAIT START state upon completion.

What is the minimum VCC voltage required for guaranteed ADM1186-1ARQZ operation?

The ADM1186-1ARQZ guarantees valid output states (OUT1–OUT4, PWRGD, SEQ_DONE, FAULT) down to VCC = 1 V. Below 1 V, output behavior is undefined. Internal undervoltage lockout activates at 2.46 V (falling), disabling the state machine until VCC exceeds this threshold and internal references stabilize - ensuring controlled startup and preventing partial enablement of downstream regulators.

How do I configure the ADM1186-1ARQZ to monitor a 1.8 V rail?

To monitor a 1.8 V rail with the ADM1186-1ARQZ, connect it to VIN1 (or VIN2–VIN4) through an external resistor divider that scales 1.8 V down to 0.6 V at the input pin. For example, using R1 = 10 kΩ and R2 = 5 kΩ yields V_IN = 1.8 V × (5 kΩ / (10 kΩ + 5 kΩ)) = 0.6 V - setting the undervoltage threshold at 1.8 V. The comparator's ±0.8% accuracy ensures detection between 1.785 V and 1.815 V under nominal conditions.