Analog Devices Inc. ADM6320CY29ARJZ-R7

Overview

ADM6320CY29ARJZ-R7 from Analog Devices is a supervisory circuit with integrated watchdog timer and manual reset input, designed for microprocessor supply voltage monitoring and code execution integrity assurance. It features a 2.93 V reset threshold (±2.5% over −40°C to +85°C), 140 ms minimum reset timeout, 1.6 s typical watchdog timeout, open-drain active-low RESET output, and operates from 1 V to 5.5 V supply. It is used in embedded controllers where brownout detection and fail-safe recovery are critical.

For engineers reviewing the ADM6320CY29ARJZ-R7 datasheet, ADM6320CY29ARJZ-R7 pinout, ADM6320CY29ARJZ-R7 application, or ADM6320CY29ARJZ-R7 equivalent, key selection criteria include its open-drain reset configuration, industrial temperature range (−40°C to +85°C), low quiescent current (≤12 µA at 3.6 V), guaranteed reset validity down to VCC = 1 V, and compatibility with 5-lead SOT-23 PCB footprints.

Technical Context

The ADM6320CY29ARJZ-R7 implements a precision bandgap-based voltage reference for reset threshold detection with 40 ppm/°C temperature coefficient and 3 mV hysteresis. Its watchdog timer clears on any logic transition (≥50 ns pulse width) at the WDI pin and times out after 1.6 s (typical), enabling robust detection of firmware hangs.

Reset assertion occurs when VCC falls below 2.93 V, when MR is pulled low ≥1 µs, or when WDI remains static beyond the watchdog timeout. The open-drain RESET output requires an external pull-up and remains valid down to VCC = 1 V, supporting brownout-safe system recovery in portable and industrial applications.

Key Specifications

Pinout & Package

ADM6320CY29ARJZ-R7 is housed in a 5-lead SOT-23 package (JEDEC MO-178-AA compliant, 2.90 mm × 1.60 mm × 1.15 mm). Pin 1 is RESET (open-drain active-low), Pin 2 is GND, Pin 3 is MR (manual reset input, active-low, internal 52 kΩ pull-up), Pin 4 is WDI (watchdog input, edge-sensitive), and Pin 5 is VCC (monitored supply input).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with MAX6320CY29D3+T and TPS3808G33DBVR, the ADM6320CY29ARJZ-R7 uniquely combines open-drain reset flexibility, integrated watchdog with 1.6 s timeout, and guaranteed operation down to VCC = 1 V-making it optimal for multi-rail, safety-critical, or battery-depletion-prone systems.

Availability

ADM6320CY29ARJZ-R7 is available at Aetrix Electronics and suitable for industrial PLC controllers, medical handheld diagnostics, automotive body control modules, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADM6320CY29ARJZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADM63xx family was engineered specifically for robust microprocessor supervision in harsh environments, emphasizing low-power operation, glitch immunity, and flexible reset architectures for embedded control systems.

FAQ

What is the reset threshold voltage of the ADM6320CY29ARJZ-R7?

The ADM6320CY29ARJZ-R7 has a nominal reset threshold voltage of 2.93 V, with tolerance of ±2.5% over the full industrial temperature range (−40°C to +85°C). This value is factory-trimmed and specified in Table 5 of the Rev. I datasheet. The threshold is referenced to the monitored VCC supply and remains stable with a temperature coefficient of 40 ppm/°C.

Does the ADM6320CY29ARJZ-R7 support watchdog functionality?

Yes, the ADM6320CY29ARJZ-R7 includes a configurable watchdog timer with a typical timeout of 1.6 seconds (suffix Y). It monitors the WDI pin for logic transitions and asserts RESET if no edge is detected within that period. The timer clears on any rising or falling edge ≥50 ns wide and is disabled when WDI is left floating.

What type of RESET output does the ADM6320CY29ARJZ-R7 provide?

The ADM6320CY29ARJZ-R7 provides an open-drain active-low RESET output (Pin 1). This requires an external pull-up resistor to a logic-compatible voltage rail (≤6 V). The output sinks current when asserted and presents high impedance when deasserted, enabling wired-OR configurations and voltage-level translation.

What is the minimum reset timeout period for the ADM6320CY29ARJZ-R7?

The ADM6320CY29ARJZ-R7 has a minimum reset timeout period of 140 ms (suffix C), as confirmed in Table 6 and the Ordering Guide. This duration begins when VCC rises above the 2.93 V threshold and ensures sufficient hold time for microprocessor power stabilization before release.

Is the ADM6320CY29ARJZ-R7 compatible with 1.8 V logic systems?

Yes - while the ADM6320CY29ARJZ-R7 monitors a 2.93 V supply rail, its open-drain RESET output can interface directly with 1.8 V logic systems when pulled up to 1.8 V. The device itself operates from VCC = 1 V to 5.5 V and guarantees RESET validity down to VCC = 1 V, making it suitable for mixed-voltage designs.