Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Power Supply Controllers, Monitors

Analog Devices Inc. ADM6819ARJZ-REEL7

Name: ADM6819ARJZ-REEL7
Brand: Analog Devices Inc.
SKU: ADM6819ARJZ-REEL7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: ADM6819ARJZ-REEL7

Manufacturer:: Analog Devices Inc.

Category:: Power Supply Controllers, Monitors

Package:: SOT-23-6

Datasheet:: ADM6819ARJZ-REEL7.pdf

Description:: IC POWER SEQUENCER SOT23-6

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,888

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

ADM6819ARJZ-REEL7 from Analog Devices is a dual-supply power sequencing controller with integrated N-channel FET gate driver and on-chip charge pump. It monitors two independent supply rails (VCC1 and VCC2), enforces a fixed 300 ms delay between primary supply validation and secondary FET enablement, and drives external N-MOSFETs to achieve low-dropout power path control in multivoltage systems. Key confirmed parameters: 0.618 V SETV threshold, −40°C to +85°C operating range, 6-lead SOT-23 package, 300 ms fixed sequencing delay, and 2.95 V to 5.5 V supply voltage range.

For engineers reviewing the ADM6819ARJZ-REEL7 datasheet, ADM6819ARJZ-REEL7 pinout, ADM6819ARJZ-REEL7 application, or ADM6819ARJZ-REEL7 equivalent, this device serves as a precision dual-rail sequencer for FPGA, microprocessor, and telecom power domains where validated supply readiness and controlled turn-on timing are critical to system reliability.

Technical Context

The ADM6819ARJZ-REEL7 implements a dual-comparator architecture: one on the SETV pin (0.618 V threshold) for primary supply monitoring and a second identical comparator on the EN pin for secondary supply validation. Both comparators must exceed threshold before the fixed 300 ms timer initiates GATE drive activation.

Its internal charge pump generates gate drive voltage up to 9.9 V above VCCx (at 5.5 V VCCx), fully enhancing external N-channel MOSFETs without external boost components. The device operates only when at least one supply (VCC1 or VCC2) exceeds 2.95 V UVLO, and disables GATE immediately upon EN low or SETV falling below threshold.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	2.95 V to 5.5 V per supply rail - ensures operation across common logic and core rails (3.3 V, 5 V) while enforcing undervoltage lockout below 2.95 V
SETV Threshold Voltage	0.618 V ±16 mV - enables precise resistor-divider-based trip point setting for primary supply monitoring
Sequencing Delay	Fixed 300 ms (240–350 ms over temperature) - provides deterministic timing margin between supply validation and FET turn-on
GATE Drive Voltage	Up to 9.9 V above VCCx - fully enhances standard N-channel MOSFETs with V_GS(th) ≤ 4 V, minimizing R_DS(on) and conduction loss
EN Pin Function	Digital enable or secondary supply monitor (0.618 V threshold) - allows dual-rail validation before sequencing begins
Operating Temperature	−40°C to +85°C - supports industrial and telecom equipment deployment without derating
Quiescent Current	350–500 μA at 3.3 V - enables low-power sequencing in always-on subsystems

Pinout & Package

Packaged in a JEDEC-compliant 6-lead SOT-23 (RJ-6) footprint measuring 2.90 mm × 1.60 mm × 1.30 mm, the ADM6819ARJZ-REEL7 uses surface-mount assembly and supports reflow soldering per JEDEC J-STD-020.

Pin/Terminal	Circuit Role	Design Meaning
VCC1	Primary Supply Input	One of two independent supply inputs; must exceed 2.95 V UVLO to enable device operation
GND	Ground Reference	Common return for internal circuitry, comparators, and charge pump ground reference
SETV	Primary Supply Monitor Input	Accepts resistor-divider voltage from VCC1; triggers sequencing when ≥0.618 V
EN	Enable / Secondary Monitor Input	Active-high digital enable or second supply monitor (identical 0.618 V threshold); gates 300 ms timer start
GATE	N-Channel FET Gate Driver Output	Charge-pump-driven output that swings up to 9.9 V above VCCx to fully enhance external N-MOSFET
VCC2	Secondary Supply Input	Second independent supply input; used as source for secondary rail or charge pump reference

Key Features

Feature	Design Value
Dual-supply validation before sequencing	Requires both SETV > 0.618 V and EN > 0.618 V to initiate 300 ms timer - prevents secondary rail enablement unless both supplies meet threshold
Integrated charge pump gate driver	Eliminates need for external boost capacitors or charge pump ICs - directly drives N-MOSFET gate to full enhancement voltage
Fixed 300 ms sequencing delay	Guaranteed timing window (240–350 ms over temperature) - simplifies timing analysis and eliminates capacitor tolerance dependencies
Low-input-bias SETV/EN pins	10 nA typical input current - permits use of high-value resistor dividers (>1 MΩ), reducing power loss and board space
SOT-23 footprint compatibility	Pins 1–6 match MAX6819 pinout - enables drop-in replacement in existing designs using same PCB layout

Applications

FPGA Power Sequencing	Microprocessor Core/IO Rail Control
Use Scenario: Sequencing 1.2 V core and 3.3 V I/O supplies for Xilinx or Intel FPGAs requiring strict power-up order and hold-time compliance. IC Role / Device Role / Timing Role: ADM6819ARJZ-REEL7 acts as dual-rail supervisor and gate driver, validating both rails before enabling the 1.2 V core FET with fixed 300 ms delay relative to I/O rail stability. Use Value: Prevents FPGA configuration failure by ensuring I/O is powered and stable before core voltage ramp, leveraging dual-comparator validation and deterministic delay.	Use Scenario: Enabling ARM-based microprocessor core (1.1 V) only after DDR3 memory supply (1.5 V) and auxiliary rails reach regulation. IC Role / Device Role / Timing Role: ADM6819ARJZ-REEL7 monitors DDR3 supply on SETV and auxiliary rail on EN, then asserts GATE to enable core rail FET after 300 ms. Use Value: Guarantees minimum 300 ms hold time between memory rail readiness and core enablement, satisfying SoC boot timing requirements without external timing components.
Telecom Line Card Power Management	Industrial PLC Dual-Rail Startup
Use Scenario: Controlling power delivery to DSP and analog front-end (AFE) sections on a 48 V telecom line card with local 3.3 V and 12 V DC-DC outputs. IC Role / Device Role / Timing Role: ADM6819ARJZ-REEL7 validates 3.3 V DSP supply on SETV and 12 V AFE supply on EN, then drives N-FET to enable 1.8 V AFE core rail. Use Value: Ensures AFE analog circuitry is powered only after DSP firmware initialization completes, using dual-supply validation and fixed delay to prevent signal corruption.	Use Scenario: Sequencing 24 V field bus interface and 5 V controller logic in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: ADM6819ARJZ-REEL7 monitors 24 V bus on SETV and 5 V controller supply on EN, enabling isolation FET for 3.3 V logic rail after 300 ms. Use Value: Delivers robust startup under wide-temperature industrial conditions (−40°C to +85°C) with no timing drift from external RC networks.

FPGA Power Sequencing

Microprocessor Core/IO Rail Control

Use Scenario: Sequencing 1.2 V core and 3.3 V I/O supplies for Xilinx or Intel FPGAs requiring strict power-up order and hold-time compliance.

IC Role / Device Role / Timing Role: ADM6819ARJZ-REEL7 acts as dual-rail supervisor and gate driver, validating both rails before enabling the 1.2 V core FET with fixed 300 ms delay relative to I/O rail stability.

Use Value: Prevents FPGA configuration failure by ensuring I/O is powered and stable before core voltage ramp, leveraging dual-comparator validation and deterministic delay.

Use Scenario: Enabling ARM-based microprocessor core (1.1 V) only after DDR3 memory supply (1.5 V) and auxiliary rails reach regulation.

IC Role / Device Role / Timing Role: ADM6819ARJZ-REEL7 monitors DDR3 supply on SETV and auxiliary rail on EN, then asserts GATE to enable core rail FET after 300 ms.

Use Value: Guarantees minimum 300 ms hold time between memory rail readiness and core enablement, satisfying SoC boot timing requirements without external timing components.

Telecom Line Card Power Management

Industrial PLC Dual-Rail Startup

Use Scenario: Controlling power delivery to DSP and analog front-end (AFE) sections on a 48 V telecom line card with local 3.3 V and 12 V DC-DC outputs.

IC Role / Device Role / Timing Role: ADM6819ARJZ-REEL7 validates 3.3 V DSP supply on SETV and 12 V AFE supply on EN, then drives N-FET to enable 1.8 V AFE core rail.

Use Value: Ensures AFE analog circuitry is powered only after DSP firmware initialization completes, using dual-supply validation and fixed delay to prevent signal corruption.

Use Scenario: Sequencing 24 V field bus interface and 5 V controller logic in programmable logic controllers deployed in factory automation environments.

IC Role / Device Role / Timing Role: ADM6819ARJZ-REEL7 monitors 24 V bus on SETV and 5 V controller supply on EN, enabling isolation FET for 3.3 V logic rail after 300 ms.

Use Value: Delivers robust startup under wide-temperature industrial conditions (−40°C to +85°C) with no timing drift from external RC networks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-supply sequencing applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX6819EUT+T	Pin-to-pin compatible; identical 300 ms delay, 0.618 V threshold, and SOT-23-6 package; same dual-comparator architecture but different charge pump voltage specs (up to 8.5 V vs. 9.9 V)	Valid for legacy designs using Maxim parts; requires verification of gate drive margin for high-V_TH N-MOSFETs due to lower max GATE voltage	Select when redesigning into existing Maxim-based layouts or when sourcing constraints favor Maxim distribution channels
TPS3808G33DBVR	Single-supply supervisor only (no EN pin for secondary monitoring); adjustable delay via external capacitor; no integrated charge pump - requires external level-shifting for N-FET drive	Limited to single-rail sequencing; cannot validate two supplies before enabling output; needs additional components for N-FET gate drive	Choose only if dual-supply validation is unnecessary and external timing components are acceptable

Compared with MAX6819EUT+T and TPS3808G33DBVR, the ADM6819ARJZ-REEL7 uniquely delivers guaranteed dual-supply validation, fixed 300 ms timing, and self-contained charge-pump gate drive - eliminating external components and enabling true dual-rail sequencing in a single SOT-23 package.

Availability

ADM6819ARJZ-REEL7 is available at Aetrix Electronics and suitable for FPGA power sequencing, microprocessor core/IO rail control, telecom line card power management, industrial PLC dual-rail startup, and network processor supply coordination requiring stable component supply and long-term industrial lifecycle support.

Supply support for ADM6819ARJZ-REEL7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, serving industrial, automotive, communications, and healthcare markets.

The ADM6819ARJZ-REEL7 belongs to Analog Devices' Simple Sequencers® family, designed specifically for reliable, low-component-count power supply sequencing in multivoltage embedded systems where dual-rail validation and deterministic timing are mandatory.

FAQ

What is the function of the EN pin on the ADM6819ARJZ-REEL7?

The EN pin on the ADM6819ARJZ-REEL7 serves a dual role: it functions as either an active-high digital enable input (with 0.4 V V_IL and 2.0 V V_IH) or as a second supply monitor identical to the SETV pin (0.618 V threshold). In sequencing operation, the ADM6819ARJZ-REEL7 requires both SETV and EN to exceed 0.618 V before initiating its fixed 300 ms timer and driving the GATE output high. This ensures two independent supply rails are validated prior to enabling the secondary power path.

Does the ADM6819ARJZ-REEL7 require external components to drive an N-channel MOSFET?

No, the ADM6819ARJZ-REEL7 does not require external components to drive an N-channel MOSFET. It integrates a charge pump that generates gate drive voltage up to 9.9 V above the higher of VCC1 or VCC2, sufficient to fully enhance standard N-MOSFETs with V_GS(th) ≤ 4 V. Only the external FET and its source/drain path are needed; no boost capacitors, level shifters, or driver transistors are required for basic operation of the ADM6819ARJZ-REEL7.

What is the guaranteed sequencing delay of the ADM6819ARJZ-REEL7 over temperature?

The ADM6819ARJZ-REEL7 guarantees a sequencing delay of 240 ms to 350 ms over its full operating temperature range of −40°C to +85°C. This fixed delay is measured from the moment both SETV and EN exceed their 0.618 V thresholds until the GATE output begins rising. Unlike capacitor-adjustable alternatives, this delay is internally generated and does not depend on external component tolerances or aging, making the ADM6819ARJZ-REEL7 suitable for timing-critical applications where predictability is essential.

Can the ADM6819ARJZ-REEL7 monitor VCC2 as the primary supply instead of VCC1?

Yes, the ADM6819ARJZ-REEL7 can monitor either VCC1 or VCC2 as the primary supply - the device does not assign functional priority to either supply pin. Either VCC1 or VCC2 must exceed the 2.95 V undervoltage lockout (UVLO) threshold to enable operation, and the SETV pin can be connected to a resistor divider from whichever supply is designated as primary. The EN pin may then monitor the other supply. This flexibility allows system designers to assign roles based on rail voltage levels and sequencing requirements in the ADM6819ARJZ-REEL7 implementation.

What is the maximum gate drive voltage the ADM6819ARJZ-REEL7 can deliver relative to VCCx?

The ADM6819ARJZ-REEL7 delivers a maximum gate drive voltage of 9.9 V above the higher of VCC1 or VCC2 (VCCx = 5.5 V case), and 8.9 V above VCCx when VCCx = 2.95 V. These values are specified with RGATE > 50 MΩ to VCCx and represent the peak voltage achievable by the internal charge pump to fully enhance external N-channel MOSFETs. This capability eliminates the need for external gate drivers in most applications using standard logic-level or standard-threshold N-MOSFETs, and is a confirmed specification in the ADM6819ARJZ-REEL7 datasheet.

ADM6819ARJZ-REEL7 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: Simple Sequencers®

Package/Case:: SOT-23-6

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Applications:: Power Supply Sequencer

Voltage - Input:: -

Voltage - Supply:: 0.9V ~ 5.5V

Current - Supply:: 350 µA

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: SOT-23-6

ADM6819ARJZ-REEL7 FAQ

1.How can I place an order for ADM6819ARJZ-REEL7 through Aetrix?

Please submit a Request for Quotation (RFQ) for ADM6819ARJZ-REEL7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADM6819ARJZ-REEL7 reliable?

The price and inventory of ADM6819ARJZ-REEL7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADM6819ARJZ-REEL7 is usually 5 days.

3.What payment methods are accepted for ADM6819ARJZ-REEL7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADM6819ARJZ-REEL7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADM6819ARJZ-REEL7?

ADM6819ARJZ-REEL7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADM6819ARJZ-REEL7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADM6819ARJZ-REEL7?

For technical support, including ADM6819ARJZ-REEL7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADM6819ARJZ-REEL7 requirements.

6.How does Aetrix verify that ADM6819ARJZ-REEL7 is sourced from the original manufacturer or authorized distributors?

All ADM6819ARJZ-REEL7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADM6819ARJZ-REEL7 meets industry standards.

7.What is the process for return or replacement of ADM6819ARJZ-REEL7?

All ADM6819ARJZ-REEL7 units undergo pre-shipment inspection (PSI). If there is an issue with ADM6819ARJZ-REEL7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADM6819ARJZ-REEL7 part is unused and in its original packaging.

Return procedure for ADM6819ARJZ-REEL7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…