Analog Devices Inc. ADM691AARU

Overview

ADM691AARU from Analog Devices is a microprocessor supervisory circuit integrating power-on reset, battery backup switchover, watchdog timer, chip enable gating, and power-fail detection. It features a 4.65 V ±3% reset threshold, 200 ms or adjustable reset timeout, 1.6 s/100 ms selectable watchdog timeout, and operates with VCC as low as 1 V. It is used in industrial controllers and automotive ECUs for reliable power monitoring and data retention during brownouts.

For engineers reviewing the ADM691AARU datasheet, ADM691AARU pinout, ADM691AARU application, or ADM691AARU equivalent, key selection considerations include its TSSOP-16 package, dual reset outputs (active-low and active-high), battery switchover hysteresis of 60 mV, and compatibility with 5 V ±5% supplies - critical for embedded systems requiring deterministic reset behavior and RAM write protection.

Technical Context

The ADM691AARU implements a precision voltage detector with 4.65 V threshold and 15 mV hysteresis, ensuring stable reset assertion during VCC transitions. Its internal oscillator supports fixed (200 ms / 1.6 s) or capacitor-adjustable timing, while the watchdog transition detector responds to both rising and falling edges on WDI to prevent false timeouts.

Battery switchover uses dual PMOS/NMOS switches: a 0.8–1.2 Ω VCC-to-VOUT path (250 mA capable) and a 12–25 Ω VBATT-to-VOUT path (5–20 mA typical), enabling seamless CMOS RAM backup with <1 µA standby current. CE gating provides sub-10 ns propagation delay and 40–150 Ω ON-resistance, actively disabling memory writes during undervoltage events.

Key Specifications

Pinout & Package

RU-16 TSSOP package (4.4 mm × 5.0 mm, 0.65 mm pitch), thermally optimized for space-constrained industrial PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX691ACPE+ and TPS3823MPW, the ADM691AARU uniquely combines battery switchover, dual reset outputs, and field-adjustable watchdog timing in a single RU-16 TSSOP package - eliminating three discrete components while reducing board area by 65% and enabling deterministic fail-safe behavior in safety-critical embedded systems.

Availability

ADM691AARU is available at Aetrix Electronics and suitable for industrial PLC controllers, automotive body control modules, medical infusion pumps, and telecom remote terminal units requiring stable component supply and long-term lifecycle support.

Supply support for ADM691AARU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The ADM691AARU belongs to Analog Devices' microprocessor supervisory product line, designed specifically for robust power monitoring, data integrity protection, and fail-safe operation in mission-critical embedded systems operating across –40°C to +85°C.

FAQ

What is the reset threshold voltage of the ADM691AARU and how tightly is it specified?

The ADM691AARU has a guaranteed reset threshold of 4.65 V with ±3% tolerance (4.50 V to 4.75 V). This specification is tested over the full –40°C to +85°C industrial temperature range and ensures reliable reset assertion for +5 V systems with ±5% supply tolerance. The 15 mV hysteresis prevents chatter during slow VCC ramps, and the device continues functioning down to VCC = 1 V to maintain reset hold during deep brownouts.

Can the ADM691AARU support both fixed and adjustable reset and watchdog timing?

Yes, the ADM691AARU supports both fixed and adjustable timing through its OSC SEL and OSC IN pins. With both pins floating, it defaults to 200 ms reset timeout and 1.6 s watchdog timeout. Pulling OSC IN low selects 100 ms watchdog timeout. Connecting OSC SEL to ground enables external timing: a capacitor on OSC IN sets both periods linearly (T_reset = 1200 × C/47 pF), while an external clock sets them inversely (T_reset = 2048/f_CLK). This flexibility makes the ADM691AARU adaptable across diverse firmware timing requirements without hardware changes.

How does the ADM691AARU handle battery backup switchover and what is its quiescent current in that mode?

The ADM691AARU automatically switches VOUT from VCC to VBATT when VCC falls below VBATT + 0.03 V, with 60 mV hysteresis to prevent oscillation. In battery backup mode, it draws only 0.04–1 µA (typical 0.04 µA at +25°C), enabling multi-year operation from a 3.6 V lithium battery. The VBATT-to-VOUT path uses a low-leakage MOSFET with 12–25 Ω resistance, delivering up to 20 mA to CMOS RAM while maintaining >2.0 V output under load - verified in Table I and Figure 3 of the datasheet.

What is the function of the dual RESET outputs on the ADM691AARU and how are they electrically different?

The ADM691AARU provides two independent reset outputs: pin 15 (RESET) is active-low, open-drain; pin 16 (RESET) is active-high, also open-drain. Both are asserted simultaneously during undervoltage but differ in polarity and internal connection - pin 15 connects to the primary reset generator, while pin 16 is its logical complement. This eliminates external inverters in systems using mixed logic families (e.g., TTL RESET inputs alongside CMOS µPs), and both outputs remain functional down to VCC = 1 V, ensuring fail-safe behavior across the full operating range.

Does the ADM691AARU provide memory write protection and how is it implemented?

Yes, the ADM691AARU implements hardware-enforced memory write protection via its CEIN/CEOUT gating function. When VCC is above 4.65 V, CEOUT is a buffered replica of CEIN with 6–10 ns delay. When VCC drops below threshold, CEOUT is forced high regardless of CEIN state - blocking write access to battery-backed CMOS RAM or EEPROM. This is achieved with an internal analog switch and logic gate, not software, ensuring immunity to processor lockup. The feature is validated in Figure 17 timing diagrams and Application Information section.