Analog Devices Inc. ADM697AN

Overview

ADM697AN from Analog Devices is a microprocessor supervisory circuit with integrated chip-enable (CE) gating, watchdog timer, low-line voltage monitoring, and power-fail detection. It operates from 3.0 V to 5.5 V VCC, asserts RESET down to 1 V, provides 5 ns CE propagation delay, and features adjustable watchdog timeout (100 ms or 1.6 s). It is used in embedded controllers and industrial systems requiring reliable RAM write protection during brownout.

For engineers reviewing the ADM697AN datasheet, ADM697AN pinout, ADM697AN application, or ADM697AN equivalent, this page delivers verified functional identity, exact pin roles, real-world timing behavior, battery-backed CE gating design meaning, and validated alternative options for supervisory IC selection in safety-critical power monitoring.

Technical Context

The ADM697AN implements dual-reset logic: active-low RESET and active-high RESET outputs triggered by LLIN falling below 1.3 V, with 50 ms minimum pulse width and 12 mV comparator hysteresis. Its CE gating path-CEIN → CEOUT-has 5 ns typical propagation delay and forces CEOUT high when LLIN < 1.3 V, preventing writes to battery-backed RAM.

Watchdog operation uses a three-level WDI input (internally biased to 38% VCC); timeout defaults to 1.6 s after reset, then switches to 100 ms on first WDI transition. OSC SEL selects internal oscillator (10.24 kHz nominal) or external clock/capacitor timing; PFI and LLIN share the same 1.3 V reference but differ by ±15 mV in threshold matching.

Key Specifications

Pinout & Package

ADM697AN is supplied in a 16-pin plastic DIP (N-16) package with 0.3-inch body width and through-hole mounting. Pin 1 is TEST (must be grounded), pin 5 is GND, and pin 12 is CEOUT - the gated chip-enable output critical for RAM write protection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX697CPD+, ADM697AN offers superior noise immunity via wider LLIN hysteresis and explicit TEST pin control; versus TPS3823MPW, it delivers full system-level supervision including fail-safe CE gating - essential for data-critical applications.

Availability

ADM697AN is available at Aetrix Electronics and suitable for industrial controllers, automotive infotainment systems, and medical diagnostic equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for ADM697AN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and control.

The ADM697AN belongs to Analog Devices' microprocessor supervisory IC product line, designed specifically to ensure data integrity and deterministic reset behavior in mission-critical embedded systems with battery-backed memory.

FAQ

What is the function of the TEST pin on the ADM697AN?

The TEST pin (Pin 1) is a dedicated manufacturing test node that must be connected to GND in all operational circuits. Leaving it floating or driving it high may cause undefined behavior, including incorrect CEOUT assertion or spurious RESET pulses. The ADM697AN datasheet explicitly requires grounding TEST to ensure proper CE gating, watchdog timing, and low-line detection functionality - this is not optional for production use.

How does the ADM697AN prevent writes to RAM during power failure?

The ADM697AN prevents RAM writes during power failure by forcing CEOUT (Pin 12) high whenever LLIN falls below 1.3 V - independent of CEIN state. This action blocks chip-enable signals to battery-backed CMOS RAM or EEPROM. With 5 ns propagation delay and guaranteed operation down to 1 V VCC, ADM697AN ensures zero write window even during rapid brownout, preserving data integrity without external logic.

Can the ADM697AN watchdog timer be disabled in-circuit?

Yes, the ADM697AN watchdog timer can be disabled by leaving WDI (Pin 11) floating or biasing it to ~38% of VCC (midsupply). The internal 125 kΩ impedance and three-level input architecture ensure reliable disable behavior. Driving WDI continuously high or low will trigger timeout; only true float or midsupply bias disables the timer - confirmed by functional testing in the ADM697AN datasheet Figure 3 timing diagrams.

What is the maximum continuous output current supported by ADM697AN's CEOUT pin?

The CEOUT pin (Pin 12) of the ADM697AN supports 800 µA source current at VCC – 0.5 V and 1.6 mA sink current at 0.4 V - sufficient to directly drive standard CMOS RAM CE inputs or TTL-compatible buffers. It is not intended to supply power; its role is strictly logic-level gating. For higher-current loads, an external buffer or transistor stage is required - the ADM697AN datasheet specifies these limits under "CHIP ENABLE GATING" section with test conditions.

Does the ADM697AN support both 3.3 V and 5 V microprocessor systems?

Yes, the ADM697AN supports both 3.3 V and 5 V systems: its VCC operating range is 3.0 V to 5.5 V, LLIN and PFI thresholds are specified at both 3 V and 5 V, and RESET output remains valid down to 1 V VCC. The 1.3 V internal reference is ratiometrically stable across this range, enabling accurate voltage monitoring without recalibration - confirmed by parameter tables and Figures 10–13 in the ADM697AN datasheet.