Analog Devices Inc. ADM697ANZ

Overview

ADM697ANZ from Analog Devices is a microprocessor supervisory circuit with integrated chip-enable gating, 1.3 V low-line detection, adjustable watchdog timer (100 ms / 1.6 s), power-fail warning, and reset assertion down to 1 V VCC. It provides CEOUT-controlled write protection for battery-backed CMOS RAM in embedded controllers and industrial instrumentation.

For engineers reviewing the ADM697ANZ datasheet, ADM697ANZ pinout, ADM697ANZ application, or ADM697ANZ equivalent, key selection considerations include its 5 ns CE propagation delay, dual reset outputs (active-low RESET and active-high RESET), battery backup mode behavior, and OSC SEL–controlled timing configuration across temperature (–40°C to +85°C).

Technical Context

The ADM697ANZ implements a dual-threshold comparator for LLIN (1.3 V ±50 mV) with ~12 mV hysteresis, enabling robust power-on and brownout reset generation. Its watchdog timer supports three modes: internal oscillator (100 ms or 1.6 s), external clock (4097/1025 cycles), or external capacitor (adjustable via C/47 pF scaling).

CEIN-to-CEOUT gating operates with 5 ns typical propagation delay and forces CEOUT high during low-line conditions, preventing writes to memory when VCC drops below valid operating range. In battery backup mode (VCC = 0 V), CEIN and WDI are internally disconnected, CEOUT and RESET are held high and low respectively, and supply current drops to 0.6 µA.

Key Specifications

Pinout & Package

ADM697ANZ is housed in a 16-pin plastic DIP (N-16) package with 0.3-inch body width and through-hole mounting. Pin 1 is TEST (must be grounded), pin 5 is GND, and pin 12 is CEOUT - the gated chip-enable output critical for memory write protection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX697CPD+, ADM697ANZ offers wider LLIN threshold tolerance and lower backup current (0.6 µA vs. 1.2 µA); compared with TPS3823MPW, ADM697ANZ adds essential CE gating, PFI detection, and battery-aware operation-making it irreplaceable in memory-critical embedded systems.

Availability

ADM697ANZ is available at Aetrix Electronics and suitable for industrial controllers, automotive telematics modules, and medical handheld devices requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for ADM697ANZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and control.

The ADM697 belongs to Analog Devices' microprocessor supervisory product line, designed specifically for robust power monitoring, memory write protection, and watchdog supervision in mission-critical embedded systems operating across –40°C to +85°C.

FAQ

What is the function of the TEST pin on the ADM697ANZ?

The TEST pin (Pin 1) on the ADM697ANZ is a dedicated manufacturing test terminal used during wafer sort and final test. It must be connected to GND in all application circuits. It has no functional role in normal operation, and leaving it floating may cause undefined behavior. The ADM697ANZ will not operate correctly unless TEST is tied to ground per the datasheet requirement.

How does the ADM697ANZ handle CE gating during battery backup mode?

In battery backup mode (VCC = 0 V), the ADM697ANZ isolates CEIN from internal circuitry and forces CEOUT high regardless of CEIN state. This ensures write protection of battery-backed RAM even when main power is lost. CEOUT remains at VOUT potential (~VBATT), and the 5 ns propagation delay specification no longer applies-CEOUT is statically asserted high to prevent any memory writes during backup operation.

Can the ADM697ANZ watchdog timer be disabled, and how?

Yes, the ADM697ANZ watchdog timer can be disabled by floating the WDI pin or biasing it to approximately 38% of VCC (midsupply). When WDI is left unconnected, internal biasing holds it near midsupply, disabling watchdog supervision. Driving WDI continuously high or low also disables the timer-but this method risks accidental activation if noise causes transitions. Floating remains the recommended disable method per the datasheet.

What is the maximum continuous output current supported by the ADM697ANZ's VOUT pin?

The ADM697ANZ does not provide a VOUT pin-this function is exclusive to the ADM696 variant. The ADM697ANZ lacks battery switchover circuitry and VOUT output entirely. Its pinout replaces VOUT with CEIN (Pin 13) and CEOUT (Pin 12). Attempting to connect a load to a nonexistent VOUT on ADM697ANZ will result in incorrect operation; users requiring VOUT must select ADM696ANZ instead.

How does the OSC SEL pin affect reset and watchdog timing on the ADM697ANZ?

The OSC SEL pin on the ADM697ANZ selects the timing source: when high or floating, the internal oscillator sets both reset delay (50 ms default) and watchdog timeout (100 ms or 1.6 s depending on OSC IN state); when low, OSC IN accepts an external clock or capacitor to adjust both periods proportionally. This single pin synchronizes reset and watchdog timing, eliminating mismatched timeouts that could cause spurious resets in time-critical firmware.