Analog Devices Inc. ADM697AQ

Overview

ADM697AQ from Analog Devices is a microprocessor supervisory circuit with integrated chip-enable gating, 1.3 V low-line detection, adjustable watchdog timer (100 ms / 1.6 s), power-fail warning (PFI/PFO), and reset generation down to 1 V VCC. It provides CEOUT-controlled write protection for battery-backed CMOS RAM in industrial controllers and embedded systems requiring reliable power monitoring and memory integrity.

For engineers reviewing the ADM697AQ datasheet, ADM697AQ pinout, ADM697AQ application, or ADM697AQ equivalent, this page delivers verified functional identity, exact pin roles, real-world timing behavior, battery backup interaction, and validated alternative options - all grounded in the official Analog Devices ADM696/ADM697 Rev. 0 datasheet.

Technical Context

The ADM697AQ implements dual-reset logic (active-low RESET and active-high RESET) with 50 ms timeout, a three-level WDI input (internally biased to 38% VCC, ~125 kΩ impedance), and independent PFI comparator referenced to 1.3 V ±15 mV. Its CEIN-to-CEOUT path features 5 ns propagation delay and automatic high-force during LLIN undervoltage.

It supports three watchdog modes: internal oscillator (100 ms or 1.6 s), external clock (4097/1025 cycles), or external capacitor (e.g., 47 pF → 1.6 s). In battery backup mode (VCC = 0 V), CEIN and WDI are internally disconnected, CEOUT and RESET are forced high and low respectively, and supply current drops to 0.6 µA typical.

Key Specifications

Pinout & Package

ADM697AQ is supplied in a 16-pin CERDIP (Q-16) package with 0.3-inch body width, 100°C/W θJA thermal resistance, and -40°C to +85°C industrial temperature rating.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX697CPE+, ADM697AQ offers tighter 1.3 V LLIN threshold tolerance and lower 0.6 µA backup current; versus TPS3823-33DBVR, it delivers full feature integration (CE gating, PFI, battery-aware operation) absent in the TI part.

Availability

ADM697AQ is available at Aetrix Electronics and suitable for industrial controllers, automotive telematics modules, medical instrumentation, smart grid meters, and embedded data loggers requiring stable component supply across extended temperature and long product lifecycles.

Supply support for ADM697AQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The ADM697AQ belongs to Analog Devices' microprocessor supervisory product line, designed specifically to integrate power monitoring, memory write protection, and watchdog functionality into a single robust IC for mission-critical embedded systems.

FAQ

What is the primary function of the ADM697AQ in a microprocessor system?

The ADM697AQ serves as an integrated supervisory circuit that provides power-on/power-down reset generation, low-line voltage monitoring (LLIN), watchdog timer supervision, power-fail warning (PFI/PFO), and chip-enable (CE) gating for battery-backed RAM. Its core role is ensuring system reliability by preventing invalid memory writes and forcing controlled processor reset during supply anomalies - all within a single 16-pin Q-16 package.

How does the ADM697AQ handle CEOUT during a low-line condition?

When the voltage on the LLIN pin falls below 1.3 V, the ADM697AQ forces CEOUT high regardless of CEIN state - effectively disabling write access to connected CMOS RAM. This action begins immediately upon threshold crossing and persists until LLIN rises above 1.3 V. CEOUT resumes tracking CEIN only after the low-line condition clears, ensuring memory integrity during brownout events.

Can the ADM697AQ operate with VCC below 3.0 V?

No - the ADM697AQ requires VCC between 3.0 V and 5.5 V for normal operation. However, its RESET output remains functional down to VCC = 1 V, allowing it to assert a valid reset signal during deep brownout. Below 3.0 V, internal circuits (including CE gating and watchdog) cease operation, but the reset generator continues asserting RESET until VCC reaches 1 V.

What is the significance of the TEST pin (Pin 1) on the ADM697AQ?

Pin 1 (TEST) is a factory test node used exclusively during wafer sort and final test. It has no user-accessible function in application circuits. Analog Devices specifies that TEST must be connected to GND in all production designs to ensure correct internal biasing and avoid undefined behavior. Leaving it floating may cause erratic reset or CEOUT behavior.

Does the ADM697AQ support external capacitor-based watchdog timing?

Yes - when OSC SEL (Pin 13) is held low, the ADM697AQ accepts an external capacitor between OSC IN (Pin 12) and GND to set both reset timeout and watchdog period. For example, a 47 pF capacitor yields a nominal 1.6 s watchdog timeout and 50 ms reset pulse width. The relationship follows F_OSC (Hz) = 184,000 / C(pF), enabling precise adjustment across decades of timing range.