Analog Devices Inc. ADM697AR

Overview

ADM697AR from Analog Devices is a microprocessor supervisory circuit with integrated chip-enable gating, 1.3 V low-line detection, adjustable watchdog timer (100 ms / 1.6 s), power-fail warning (PFI/PFO), and active-high/active-low RESET outputs. It operates from 3.0 V to 5.5 V VCC, asserts RESET down to 1 V, and delivers 5 ns CE propagation delay for CMOS RAM write protection in embedded controllers.

For engineers reviewing the ADM697AR datasheet, ADM697AR pinout, ADM697AR application, or ADM697AR equivalent, this page provides verified functional identity, exact pin roles, battery-backed memory protection timing, watchdog timeout configuration options, and real-world substitution guidance for industrial microprocessor power monitoring designs.

Technical Context

The ADM697AR implements dual-reset architecture: an active-low RESET output triggered by LLIN < 1.3 V (with 50 ms pulse width) and an active-high RESET complement. Its CEIN-to-CEOUT gating path features 5 ns propagation delay and forces CEOUT high during low-line conditions to prevent invalid writes to battery-backed RAM.

Watchdog operation supports three modes: internal oscillator (100 ms short / 1.6 s long), external clock input (4097/1025 cycles), or external capacitor timing (e.g., 400 ms × C/47 pF). The WDI input is a three-level interface with ~125 kΩ impedance and internal 38% VCC bias-disabled when floating or at midsupply.

Key Specifications

Pinout & Package

ADM697AR is housed in a 16-pin SOIC (R-16) package with 1.27 mm pitch, JEDEC MS-012AC compliant, and rated for –40°C to +85°C operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX697CSA+ and TPS3823-33DBVR, the ADM697AR uniquely integrates hardware-enforced RAM write blocking, dual-mode watchdog timing, and independent power-fail interrupt generation - making it irreplaceable in designs requiring guaranteed data integrity during supply transients.

Availability

ADM697AR is available at Aetrix Electronics and suitable for industrial controllers, automotive body electronics, medical devices, point-of-sale terminals, and embedded instrumentation requiring stable component supply with guaranteed long-term availability.

Supply support for ADM697AR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and control.

The ADM697AR belongs to Analog Devices' microprocessor supervisory IC product line, engineered specifically for robust power monitoring, battery-backed memory protection, and fail-safe system initialization in harsh industrial and automotive environments.

FAQ

What is the minimum VCC voltage at which ADM697AR can assert a valid RESET signal?

The ADM697AR guarantees RESET output functionality down to 1 V VCC. At this level, the active-low RESET pin sinks 10 µA while maintaining ≤200 mV output voltage, ensuring reliable microprocessor reset hold during deep brownout conditions. This specification is validated across the full –40°C to +85°C operating range and is independent of battery backup state.

How does ADM697AR handle CEIN/CEOUT during battery backup mode?

In battery backup mode (VCC < VBATT – 0.2 V), the ADM697AR internally disconnects CEIN from its pullup and disables CE gating logic. CEOUT is forced high and held at VOUT potential, effectively blocking all memory writes. This behavior is documented in Table II of the datasheet and requires no external intervention - it occurs automatically upon switchover detection.

Can ADM697AR's watchdog timer be disabled in-circuit without modifying hardware?

Yes - the ADM697AR watchdog timer is disabled when WDI is left floating or driven to midsupply (~1.9 V at 5 V VCC). This exploits the internal 38% VCC bias and ~125 kΩ input impedance. No external components are needed; simply tri-state the driving GPIO or add a 100 kΩ pullup/pulldown to achieve midsupply. The WDO output remains high in this state.

What is the purpose of the TEST pin (Pin 1) on ADM697AR, and how should it be connected?

Pin 1 (TEST) is a factory test node with no user-accessible function. Per the datasheet Pin Function Description, it must be connected to GND in all application circuits. Leaving it unconnected may cause undefined behavior or increased susceptibility to noise, as it is not internally terminated for normal operation.

Does ADM697AR support both 3.3 V and 5 V microprocessor systems without external level shifters?

Yes - the ADM697AR operates natively from 3.0 V to 5.5 V VCC and features TTL/CMOS-compatible inputs (WDI, CEIN, OSC SEL) and outputs (RESET, CEOUT, PFO) that meet VOH/VOL specifications across this full range. Its 1.3 V LLIN threshold is ratiometric and stable, enabling direct monitoring of both 3.3 V and 5 V rails using appropriate resistor dividers without additional translation circuitry.