Analog Devices Inc. ADM697ARZ
- Part No.:
- ADM697ARZ
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
ADM697ARZ.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:126
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADM697ARZ from Analog Devices is a microprocessor supervisory circuit with integrated chip-enable gating, 1.3 V low-line detection, adjustable watchdog timer (100 ms / 1.6 s), power-fail monitoring, and reset assertion down to 1 V VCC. It serves as a system-level power integrity guardian in embedded controllers and battery-backed memory systems.
For engineers reviewing the ADM697ARZ datasheet, ADM697ARZ pinout, ADM697ARZ application, or ADM697ARZ equivalent, this page delivers verified functional identity, exact pin roles, real-world timing behavior, CE gating performance (5 ns propagation), and validated alternative options for RAM write protection and power fail supervision.
Technical Context
The ADM697ARZ implements dual independent comparators (LLIN vs. 1.3 V reference; PFI vs. 1.3 V), a configurable oscillator (internal or external clock/capacitor), and a transition-sensitive watchdog timer that resets on each WDI edge. Its CEIN-to-CEOUT path features active-high gating with automatic high-Z override when LLIN falls below threshold.
Reset generation uses a dedicated timebase with 50 ms guaranteed pulse width after LLIN recovery; watchdog timeout defaults to 1.6 s post-reset then switches to 100 ms after first WDI transition. Battery backup logic is absent (ADM696-only), confirming ADM697ARZ's exclusive focus on CE control and voltage supervision-not power switchover.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 1.3 V ±50 mV - precisely monitors 3.3 V or 5 V supply rails with hysteresis for noise immunity |
| Watchdog Timeout | 100 ms or 1.6 s (selectable) - ensures firmware liveness without requiring external timing components |
| CE Propagation Delay | 5 ns typical - enables high-speed memory write blocking during brownout without CPU cycle penalty |
| VCC Operating Range | 3.0 V to 5.5 V - supports standard industrial and computing supply rails |
| Reset Assertion Voltage | Operational down to VCC = 1 V - guarantees clean processor hold-down during deep brownout |
| PFI Input Threshold | 1.3 V ±100 mV - allows early power-fail warning via resistor divider before main supply collapse |
| Supply Current | 1.95 mA max at 100 mA load - low quiescent draw preserves system efficiency during normal operation |
Pinout & Package
ADM697ARZ is housed in a 16-lead SOIC (R-16) package with 1.27 mm pitch, RoHS-compliant, and rated for –40°C to +85°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (TEST) | Factory test pin | Must be connected to GND; no user function or signal routing |
| 2 (NC) | No-connect | Internally unconnected; leave floating per datasheet |
| 3 (VCC) | Main power supply input | Accepts 3.0–5.5 V; powers all internal circuits including CE gating logic |
| 4 (LLIN) | Low-line voltage sense input | Compares external rail to 1.3 V reference; triggers RESET/CEOUT override when below threshold |
| 5 (PFI) | Power-fail comparator input | Non-inverting input for early warning of supply decay; drives PFO low when <1.3 V |
| 6 (PFO) | Power-fail output | Active-low open-drain signal used to interrupt µP before data loss |
| 7 (WDO) | Watchdog status output | Active-low indicates watchdog timeout; resets high on next WDI transition |
| 8 (VCC) | Power supply (duplicate pin) | Second VCC connection for improved decoupling and current distribution |
| 9 (RESET) | Active-low reset output | Drives µP reset pin; held low ≥50 ms after LLIN recovers; works down to VCC = 1 V |
| 10 (GND) | Ground reference | Common return for all analog and digital functions; must be low-impedance |
| 11 (LOW LINE) | Low-line status output | Active-low mirror of LLIN comparator; immediate response (no delay) to threshold crossing |
| 12 (OSC IN) | Oscillator input | Accepts external clock (0–250 kHz) or capacitor (47 pF typical) to adjust reset/watchdog timing |
| 13 (OSC SEL) | Oscillator mode select | High/floating = internal oscillator; low = external clock/capacitor mode |
| 14 (RESET) | Active-high reset output | Inverted complement of pin 9; interfaces directly with processors requiring active-high reset |
| 15 (CEIN) | Chip-enable input | Logic input gated to CEOUT; pulled up internally (3 µA); connect to GND/VOUT if unused |
| 16 (CEOUT) | Gated chip-enable output | Tracks CEIN when LLIN >1.3 V; forced high when LLIN <1.3 V to block memory writes |
Key Features
| Feature | Design Value |
|---|---|
| Sub-1 V reset operation | Guaranteed RESET assertion at VCC = 1 V ensures deterministic shutdown even during severe brownout |
| 5 ns CE propagation delay | Enables real-time write protection of battery-backed RAM without adding CPU wait states |
| Configurable watchdog timeout | Hardware-selectable 100 ms / 1.6 s periods eliminate need for software timer calibration |
| Dual independent comparators | Separate LLIN and PFI inputs allow simultaneous brownout detection and predictive power-fail warning |
| Active-high and active-low RESET outputs | Eliminates level-shifting requirements for diverse microprocessor families |
Applications
| Industrial PLC Controller | Medical Diagnostic Instrument |
|---|---|
|
Use Scenario: Continuous operation with battery-backed SRAM storing calibration data and fault logs during AC mains interruption. IC Role / Device Role / Timing Role: ADM697ARZ monitors 3.3 V I/O rail via LLIN, gates CEOUT to freeze SRAM writes during undervoltage, and asserts RESET to halt CPU until stable power returns. Use Value: Prevents corruption of critical calibration tables by blocking writes at precisely 1.3 V, with 50 ms reset hold time ensuring full power stabilization before restart. |
Use Scenario: Portable ultrasound device with nonvolatile memory holding patient session history and transducer profiles. IC Role / Device Role / Timing Role: ADM697ARZ uses PFI to detect falling 5 V DC-DC output 10–15 ms before LLIN threshold breach, triggering controlled save-and-shutdown sequence via PFO interrupt. Use Value: Enables reliable data preservation across >10,000 power cycles by decoupling early-warning (PFI) from hard reset (LLIN), avoiding race conditions in safety-critical firmware. |
| Automotive Body Control Module | Smart Energy Meter |
|
Use Scenario: CAN-connected BCM retaining configuration settings and error counters during vehicle battery voltage sag (<8 V). IC Role / Device Role / Timing Role: ADM697ARZ watches 3.3 V LDO output via LLIN, forces CEOUT high to lock EEPROM writes, and pulses RESET to reset MCU core while keeping CAN peripheral alive. Use Value: Maintains functional safety compliance (ISO 26262) by guaranteeing memory integrity and deterministic reset behavior under ISO 16750-2 transient conditions. |
Use Scenario: Revenue-grade meter with tamper-proof flash storing tariff schedules and consumption history across grid outages. IC Role / Device Role / Timing Role: ADM697ARZ monitors 3.3 V RTC supply via LLIN and uses WDI toggled by real-time clock ISR to verify firmware execution continuity during extended blackouts. Use Value: Detects stuck firmware loops (e.g., due to EMI-induced bit flips) within 100 ms, preventing incorrect billing data accumulation during multi-hour outages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX697CSA+ | Pin-compatible but lacks CE gating; offers battery switchover (ADM696 function) instead | Requires external logic for RAM write protection; suitable only if backup switching is needed | Select only if system requires VBATT-to-VOUT switchover - ADM697ARZ provides superior CE control where memory integrity is priority |
| TPS3808G33DBVR | Fixed 3.3 V reset threshold; no adjustable watchdog; no CE gating; push-pull RESET output | Limited to single-rail monitoring; cannot replace ADM697ARZ's dual-comparator + CEIN/CEOUT architecture | Use only for basic reset supervision without memory protection or programmable timing - not a functional substitute |
Compared with MAX697CSA+ and TPS3808G33DBVR, ADM697ARZ uniquely integrates 5 ns CE gating with dual-threshold voltage supervision, enabling deterministic write blocking during brownout - a capability absent in both alternatives and essential for systems storing mission-critical data in battery-backed memory.
Availability
ADM697ARZ is available at Aetrix Electronics and suitable for industrial PLC controllers, medical diagnostic instruments, automotive body control modules, smart energy meters, and critical microprocessor power monitoring applications requiring stable component supply and long-term lifecycle support.
Supply support for ADM697ARZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets with precision power, sensing, and timing solutions.
The ADM697ARZ belongs to Analog Devices' microprocessor supervisory IC product line, engineered specifically for systems demanding robust memory write protection, predictive power-fail detection, and sub-1 V reset assurance in harsh operating environments.
FAQ
What is the primary function of the ADM697ARZ in a microprocessor system?
The ADM697ARZ serves as a supervisory circuit focused on memory integrity and power reliability. Its core functions include monitoring supply voltage via LLIN and PFI inputs, generating precise reset signals (active-low and active-high), providing watchdog timer supervision, and-uniquely-gating the CEIN signal to CEOUT with 5 ns delay to prevent writes to battery-backed RAM during brownout conditions. This makes ADM697ARZ especially valuable where data corruption must be avoided during power transitions.
Does the ADM697ARZ support battery backup switching like the ADM696?
No, the ADM697ARZ does not support battery backup switching. That function is exclusive to the ADM696 variant. The ADM697ARZ omits VBATT, VOUT, and BATT ON pins entirely - its pinout and internal architecture are optimized for chip-enable gating and voltage supervision only. If battery switchover is required, the ADM696ARZ (or equivalent) must be selected instead of ADM697ARZ.
How does the CE gating feature of the ADM697ARZ protect memory during power failure?
The ADM697ARZ monitors the LLIN input against a 1.3 V reference. When LLIN drops below threshold, the internal logic immediately forces CEOUT high - regardless of CEIN state - blocking write access to connected CMOS RAM or EEPROM. This occurs with only 5 ns propagation delay, ensuring no spurious writes occur during the earliest phase of supply decay. CEOUT returns to tracking CEIN only after LLIN rises above 1.3 V and remains stable, preserving data integrity without software intervention.
Can the watchdog timeout period of the ADM697ARZ be adjusted, and how?
Yes, the ADM697ARZ watchdog timeout is configurable via the OSC SEL and OSC IN pins. With OSC SEL high or floating, the internal oscillator sets fixed periods: 100 ms (OSC IN low) or 1.6 s (OSC IN high). With OSC SEL low, an external capacitor on OSC IN (e.g., 47 pF) yields ~1.6 s timeout, while an external clock (0–250 kHz) allows precise cycle-based timing (e.g., 1024 or 4096 cycles). All configurations maintain the 1.6 s post-reset default to ensure safe firmware initialization.
What is the minimum VCC voltage at which ADM697ARZ can assert a valid RESET signal?
The ADM697ARZ guarantees RESET assertion down to VCC = 1 V. At this voltage, the RESET output sinks ≤200 mV with 10 µA load, maintaining sufficient noise margin to hold a microprocessor in reset. This specification is verified across temperature and process corners, making ADM697ARZ suitable for applications experiencing deep brownout conditions where other supervisors may release reset prematurely - a critical requirement for fail-safe embedded systems.
ADM697ARZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 1.3V
- Output:
- Push-Pull, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- 35ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
ADM697ARZ FAQ
1.How can I place an order for ADM697ARZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ADM697ARZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADM697ARZ reliable?
The price and inventory of ADM697ARZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADM697ARZ is usually 5 days.
3.What payment methods are accepted for ADM697ARZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADM697ARZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADM697ARZ?
ADM697ARZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADM697ARZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADM697ARZ?
For technical support, including ADM697ARZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADM697ARZ requirements.
6.How does Aetrix verify that ADM697ARZ is sourced from the original manufacturer or authorized distributors?
All ADM697ARZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADM697ARZ meets industry standards.
7.What is the process for return or replacement of ADM697ARZ?
All ADM697ARZ units undergo pre-shipment inspection (PSI). If there is an issue with ADM697ARZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADM697ARZ part is unused and in its original packaging.
Return procedure for ADM697ARZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADM697ARZ Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

