Analog Devices Inc. ADM800LARN

Overview

ADM800LARN from Analog Devices is a microprocessor supervisory circuit integrating power-on reset, battery backup switchover, watchdog timer, chip enable gating, and power-fail detection. It features a 4.65 V ±2% reset threshold, 200 ms fixed reset timeout, 1.6 s long/100 ms short watchdog timeout, and supports VCC down to 1 V operation. It is used in industrial controllers and embedded systems requiring reliable power monitoring and RAM write protection.

For engineers reviewing the ADM800LARN datasheet, ADM800LARN pinout, ADM800LARN application, or ADM800LARN equivalent, key selection criteria include its precise 4.65 V reset threshold tolerance, dual-mode watchdog timing (internal oscillator or external clock/capacitor), battery switchover with <0.04 µA standby current, and integrated CE gating for CMOS RAM write protection.

Technical Context

The ADM800LARN implements a precision bandgap-based voltage detector for reset generation, with hysteresis of 15 mV and guaranteed operation down to VCC = 1 V. Its internal PMOS switch enables seamless VCC-to-VBATT switchover at VBATT + 0.03 V (power-up) and VBATT – 0.03 V (power-down), with 60 mV hysteresis.

The watchdog uses a transition-sensitive input (WDI) that resets on any high–low or low–high edge; timeout periods are configurable via OSC SEL/OSC IN to select internal 100 ms/1.6 s modes, external capacitor (T_wd = 600 × C/47 pF), or external clock (T_wd = 1024/f_CLK). The CE gating circuit forces CEOUT high during reset, independent of CEIN, ensuring RAM write disable during brownout.

Key Specifications

Pinout & Package

ADM800LARN is packaged in a 16-lead narrow SOIC (R-16N) with standard 1.27 mm pitch, RoHS-compliant, and rated for –40°C to +85°C operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with ADM691AARN, ADM800LARN eliminates dedicated BATT ON base-drive logic but retains identical reset accuracy and timing; compared with MAX691ACPE+, it reduces active current by 30% and adds capacitor- or clock-programmable watchdog periods for modern firmware safety protocols.

Availability

ADM800LARN is available at Aetrix Electronics and suitable for industrial PLC controllers, automotive body control modules, medical infusion pumps, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADM800LARN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The ADM691A/ADM693A/ADM800L/M family was designed specifically for microprocessor system reliability-integrating reset, watchdog, battery switchover, and memory protection in a single IC to replace discrete supervision solutions.

FAQ

What is the reset threshold voltage and tolerance for ADM800LARN?

The ADM800LARN has a guaranteed reset threshold of 4.65 V with ±2% tolerance over temperature and supply variations. This ensures reliable assertion of RESET when VCC falls below 4.55 V and release when VCC rises above 4.75 V, making it compatible with +5 V ±5% power supplies commonly used in industrial microprocessor systems. The threshold is derived from an internal bandgap reference and is specified across the full –40°C to +85°C operating range.

Does ADM800LARN support external timing components for the watchdog and reset functions?

Yes, ADM800LARN supports external timing via the OSC SEL and OSC IN pins. With OSC SEL grounded, connecting a capacitor from OSC IN to GND sets both watchdog timeout (T_wd = 600 × C/47 pF) and reset active period (T_reset = 1200 × C/47 pF). Alternatively, driving OSC IN with an external clock yields T_wd = 1024/f_CLK and T_reset = 2048/f_CLK. These configurations allow precise tuning beyond the default 100 ms/1.6 s internal settings.

How does ADM800LARN handle battery backup switchover and what is its standby current?

ADM800LARN automatically switches VOUT from VCC to VBATT when VCC drops below VBATT – 0.03 V (power-down) and back when VCC rises above VBATT + 0.03 V (power-up), with 60 mV hysteresis. In battery backup mode, its supply current is as low as 0.04 µA typical, enabling multi-year operation from a CR2032 coin cell. The VBATT-to-VOUT path uses a 7 Ω MOSFET, delivering up to 10 mA at low dropout, sufficient for CMOS RAM retention.

Can ADM800LARN be used to protect EEPROM or NOVRAM write operations?

Yes, ADM800LARN's CEOUT pin is explicitly designed for memory write protection. When VCC falls below the 4.65 V reset threshold, CEOUT is forced high within 12 µs-regardless of CEIN state-to disable chip select or write inputs of CMOS RAM, EEPROM, EAROM, or NOVRAM. This prevents corrupted writes during power-up, brownout, or shutdown, and is confirmed in the device's functional description and timing diagrams.

What is the function of the PFI and PFO pins on ADM800LARN?

The PFI (Power Fail Input) pin connects to a resistor divider monitoring the main power rail; it compares the divided voltage against an internal 1.25 V reference. When PFI falls below 1.25 V, the PFO (Power Fail Output) pin goes low-an open-drain signal typically routed to a microprocessor's NMI input. This provides early warning (e.g., 5–20 ms before VCC drops to 4.65 V), allowing time to save critical data before reset occurs. PFO remains active in battery backup mode as long as VCC ≥ VBATT – 1.2 V.