Analog Devices Inc. ADM805LARN
- Part No.:
- ADM805LARN
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
ADM805LARN.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADM805LARN from Analog Devices is a precision microprocessor supervisory circuit in SO-8 package, providing active-high RESET output, 4.65 V supply voltage monitoring, 200 ms reset timeout, and integrated watchdog timer with 1.6 s timeout. It delivers battery switchover for CMOS RAM backup and power-fail detection via 1.25 V PFI threshold - used in industrial controllers requiring reliable cold-start and brownout recovery.
For engineers reviewing the ADM805LARN datasheet, ADM805LARN pinout, ADM805LARN application, or ADM805LARN equivalent, key selection criteria include active-high reset polarity, guaranteed reset assertion down to 1 V VCC, ±40 mV reset threshold hysteresis, battery switchover accuracy (±20 mV), and compatibility with 3 V backup sources in space-constrained embedded systems.
Technical Context
The ADM805LARN integrates four core functions on a single die: a precision bandgap-based 4.65 V reset comparator with 40 mV hysteresis, a transition-detecting watchdog timer triggered by WDI edge transitions, a low-dropout PMOS battery switchover switch (typ. <1 Ω on-resistance), and a 1.25 V reference-based power-fail comparator with PFO open-drain output.
Its reset generator asserts active-high RESET for ≥200 ms after VCC rises above 4.65 V or after watchdog timeout; the battery switchover activates when VCC falls 20 mV below VBATT and deactivates when VCC rises 20 mV above VBATT, with 40 mV hysteresis to prevent chatter during transition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 4.65 V nominal (4.5 V min / 4.75 V max); ensures reliable reset initiation at valid +5 V supply margin. |
| Reset Timeout | 200 ms typical; provides sufficient stabilization time for microprocessors post-power-up or post-brownout. |
| Watchdog Timeout | 1.6 s nominal (1.0–2.25 s range); detects software lockup without requiring external timing components. |
| Supply Current | 100 µA max at VCC = 5 V; enables low-power operation in always-on monitoring applications. |
| Battery Backup Current | 0.05–1.0 µA; minimizes self-discharge of 3 V lithium or supercapacitor backup sources. |
| VCC Operating Range | 1.0 V to 5.5 V; guarantees RESET assertion integrity even during deep brownout down to 1 V. |
| PFI Threshold | 1.25 V ±25 mV; supports accurate power-fail warning using external resistor divider for custom trip points. |
Pinout & Package
ADM805LARN is housed in an 8-lead SOIC (SO-8) package per JEDEC MS-012, 1.27 mm pitch, 4.9 × 6.0 mm body size, with gull-wing leads and moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Main power supply input | +5 V nominal supply; powers internal circuitry and drives VOUT when above reset threshold. |
| VBATT | Backup battery input | Accepts 2.8–6 V backup source; automatically switches to VOUT when VCC drops 20 mV below VBATT. |
| VOUT | Switched output rail | Delivers VCC or VBATT (whichever higher) to RAM or low-power logic; supports 250 mA peak load in normal mode. |
| GND | Ground reference | Common return for all analog and digital functions; required for accurate 1.25 V reference and comparator operation. |
| PFI | Power-fail input | Non-inverting input to 1.25 V comparator; monitors external supply via resistor divider to trigger PFO low on undervoltage. |
| PFO | Power-fail output | Open-drain output asserted low when PFI < 1.25 V; used to generate NMI or initiate controlled shutdown. |
| WDI | Watchdog input | Three-level input (high/low/floating); resets 1.6 s timer on each edge; floating disables watchdog. |
| RESET | Active-high reset output | Complementary to RESET; driven high during reset assertion (VCC or VBATT level); sinks 3.2 mA minimum. |
Key Features
| Feature | Design Value |
|---|---|
| Active-high RESET output | Eliminates need for external inverter when interfacing with processors requiring high-active reset (e.g., ARM Cortex-M series). |
| Guaranteed reset down to 1 V VCC | Ensures deterministic processor hold during deep brownout, preventing erratic execution or memory corruption. |
| Integrated 1.25 V precision reference | Enables accurate, temperature-stable power-fail detection without external reference IC or trimming. |
| Automatic battery switchover with 40 mV hysteresis | Prevents oscillation during VCC/VBATT crossover and extends backup source life via sub-1 µA standby current. |
| Watchdog timer with edge-triggered reset | Reduces false triggers vs. level-sensitive designs; supports software-driven toggling on any GPIO without dedicated timer peripheral. |
Applications
| Industrial PLC Controller | Medical Diagnostic Instrument |
|---|---|
Use Scenario: Power monitoring and RAM retention during mains interruption in programmable logic controller modules operating in factory environments with fluctuating 24 V DC supplies. IC Role / Device Role / Timing Role: Supervisory IC providing active-high reset, battery-backed RAM power switchover, and early power-fail interrupt via PFO to save I/O state before shutdown. Use Value: Prevents configuration loss and ensures deterministic restart after brief outages using 3 V lithium coin cell with <1 µA drain during backup mode. |
Use Scenario: Ensuring data integrity in portable ultrasound devices where main battery may dip during high-current transducer bursts. IC Role / Device Role / Timing Role: Monitors regulated 5 V rail for brownout, asserts RESET to halt CPU and preserve acquired image buffers in SRAM during transient voltage sag. Use Value: Guarantees 200 ms reset pulse even if VCC collapses to 1.0 V, enabling safe memory freeze and nonvolatile storage handoff. |
| Telecom Remote Terminal Unit | Energy Meter with Tamper Detection |
Use Scenario: Maintaining real-time clock and configuration memory in outdoor RTUs powered by solar-charged LiFePO₄ batteries with wide temperature variation (−40°C to +85°C). IC Role / Device Role / Timing Role: Provides temperature-stable 4.65 V reset threshold, watchdog supervision of firmware heartbeat, and seamless switchover to backup capacitor bank during solar panel shading events. Use Value: Achieves ±2% PFI accuracy and 40 mV hysteresis to reject noise-induced false PFO assertions in electrically noisy substations. |
Use Scenario: Securing meter calibration constants and tamper logs in ANSI C12.22-compliant smart meters subjected to rapid AC line dropout and EFT bursts. IC Role / Device Role / Timing Role: Generates active-high RESET to freeze metrology ASIC registers, triggers PFO interrupt for secure log write, and maintains SRAM via VBATT during 100 ms AC dropout. Use Value: Delivers 100 µA quiescent current and 0.05 µA battery mode draw to extend 10-year lithium backup life while meeting IEC 62053-21 fault tolerance requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX805LCSA+ | Pin-compatible Maxim replacement; same 4.65 V threshold, 200 ms timeout, and active-high RESET; 120 µA max supply current vs. 100 µA for ADM805LARN. | Requires identical PCB layout; supports same SO-8 footprint and VCC/VBATT interface but lacks specified PFI accuracy guarantee (±25 mV vs. ADM805LARN's documented ±25 mV). | Select when sourcing from Maxim-authorized channels; verify PFI tolerance meets system noise margin requirements. |
| TPS3808G16DBVR | Texas Instruments device with 4.63 V threshold (±0.5%), 200 ms delay, and active-high RESET; adds manual reset input (MR) and lower 16 µA quiescent current. | Includes MR pin for external reset initiation - useful for front-panel reset buttons - but requires additional board routing and lacks integrated battery switchover. | Choose when manual reset capability is needed and battery backup is handled externally; not drop-in due to missing VBATT/VOUT functionality. |
Compared with MAX805LCSA+, ADM805LARN offers tighter supply current spec (100 µA vs. 120 µA) and confirmed ±25 mV PFI tolerance; versus TPS3808G16DBVR, it integrates battery switchover and PFO comparator but consumes more quiescent power and lacks MR input - making ADM805LARN optimal for compact, self-contained backup systems.
Availability
ADM805LARN is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, telecom infrastructure, and smart metering applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ADM805LARN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision measurement and control.
The ADM690A/ADM802L/M/ADM805L/M family was designed specifically for robust microprocessor supervision in harsh industrial and instrumentation environments, emphasizing fail-safe reset behavior, battery autonomy, and noise-immune power-fail detection.
FAQ
What is the reset polarity of the ADM805LARN?
ADM805LARN features an active-high RESET output, which is the complement of the active-low RESET signal found on other members of the family like ADM690A. This allows direct connection to microprocessors that require a high-asserted reset signal without external inversion circuitry. The ADM805LARN RESET pin drives high during reset assertion and remains high for the full 200 ms timeout period, with output voltage equal to the higher of VCC or VBATT.
Does the ADM805LARN support battery backup for CMOS RAM?
Yes, ADM805LARN provides fully integrated battery switchover functionality. When VCC falls below the reset threshold and drops 20 mV below VBATT, the internal PMOS switch connects VBATT to VOUT to maintain power to attached CMOS RAM. The switchover includes 40 mV hysteresis to prevent oscillation, and the device draws only 0.05–1.0 µA in battery backup mode - compatible with standard 3 V lithium coin cells or high-capacity supercapacitors.
What is the guaranteed operating voltage range for VCC on the ADM805LARN?
The ADM805LARN guarantees functional operation over a VCC range of 1.0 V to 5.5 V. Critically, the RESET output remains asserted (high) even as VCC decays down to 1.0 V, ensuring reliable microprocessor hold during deep brownout conditions. This specification is validated across the full industrial temperature range (−40°C to +85°C) and is not dependent on external components or configuration.
How does the watchdog timer on the ADM805LARN operate?
The ADM805LARN watchdog timer has a nominal timeout period of 1.6 seconds and is edge-triggered via the WDI pin: each rising or falling transition resets the timer. If no transition occurs within 1.6 s, RESET is asserted high for 200 ms. The timer is disabled when WDI is left floating or connected to a high-impedance (three-state) driver - eliminating need for software initialization or configuration registers.
Can the ADM805LARN monitor a power supply other than +5 V?
Yes, the ADM805LARN includes a dedicated power-fail comparator with a precise 1.25 V internal reference. By connecting an external resistor divider from the target supply rail to the PFI pin, users can configure custom undervoltage trip points - for example, detecting failure of a +3.3 V or +12 V rail. The PFO output goes low when PFI falls below 1.25 V, enabling interrupt-driven shutdown or logging before complete power loss.
ADM805LARN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Push-Pull, Totem Pole
- Reset:
- Active High
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
ADM805LARN FAQ
1.How can I place an order for ADM805LARN through Aetrix?
Please submit a Request for Quotation (RFQ) for ADM805LARN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADM805LARN reliable?
The price and inventory of ADM805LARN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADM805LARN is usually 5 days.
3.What payment methods are accepted for ADM805LARN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADM805LARN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADM805LARN?
ADM805LARN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADM805LARN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADM805LARN?
For technical support, including ADM805LARN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADM805LARN requirements.
6.How does Aetrix verify that ADM805LARN is sourced from the original manufacturer or authorized distributors?
All ADM805LARN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADM805LARN meets industry standards.
7.What is the process for return or replacement of ADM805LARN?
All ADM805LARN units undergo pre-shipment inspection (PSI). If there is an issue with ADM805LARN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADM805LARN part is unused and in its original packaging.
Return procedure for ADM805LARN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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