Analog Devices Inc. ADM8691AN
- Part No.:
- ADM8691AN
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
ADM8691AN.pdf
- Description:
- IC SUPERVSR MPU 4.65V ADJ 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:5,711
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADM8691AN from Analog Devices is a 16-lead TSSOP microprocessor supervisory circuit providing precision reset generation (50 ms or adjustable), 4.65 V VCC monitoring, watchdog timeout selection (100 ms/1.6 s/adjustable), automatic battery backup switchover, and CE gating for RAM write protection. It operates across −40°C to +85°C and supports 5 V systems with brownout immunity down to 1 V.
For engineers reviewing the ADM8691AN datasheet, ADM8691AN pinout, ADM8691AN application, or ADM8691AN equivalent, this page delivers verified functional roles, real-world timing behavior, battery switchover thresholds, CE propagation delay (3 ns), and design-meaningful parameter values - all confirmed from Analog Devices Rev. C datasheet.
Technical Context
The ADM8691AN integrates a precision 4.65 V reset threshold comparator with 40 mV hysteresis, an internal oscillator selectable between 100 ms and 1.6 s watchdog periods (or externally adjustable via OSC IN), and dual-mode battery switchover logic that activates at VCC − VBATT = 70 mV (rising) and 50 mV (falling), with 20 mV hysteresis.
Its CEIN-to-CEOUT path provides 3 ns propagation delay with active-high gating: CEOUT tracks CEIN only when VCC ≥ 4.65 V; below threshold, CEOUT is forced high to prevent writes to battery-backed RAM. The WDO output asserts low on watchdog timeout and resets on next WDI transition or LOW LINE assertion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 4.65 V nominal; guarantees reset assertion for 5 V ±5% supplies; min/max 4.5 V/4.73 V ensures compatibility with industrial 5 V rails. |
| Reset Pulse Width | 50 ms typical (adjustable); provides sufficient stabilization time for microprocessors after power-up or brownout recovery. |
| Watchdog Timeout | 100 ms or 1.6 s fixed, or adjustable via external capacitor/clock; enables flexible firmware supervision without hardware redesign. |
| Battery Switchover | VCC − VBATT = 70 mV (rise), 50 mV (fall); hysteresis prevents oscillation during slow VCC decay near battery voltage. |
| CE Propagation Delay | 3 ns max; enables real-time write protection of CMOS RAM during supply collapse without timing margin loss. |
| Supply Current | 200 μA typical (normal), 0.4 μA in battery backup; minimizes drain on backup batteries during extended power loss. |
| VOUT Drive Capability | 100 mA max at <0.2 V dropout; powers CMOS RAM directly without external pass transistor under full load. |
Pinout & Package
ADM8691AN is housed in a 16-lead TSSOP package (4.4 mm × 5.0 mm, 0.65 mm pitch), RoHS-compliant and rated for industrial temperature range (−40°C to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBATT (Pin 1) | Backup Battery Input | Accepts 2.0–4.25 V battery; internally selected over VCC when VCC drops below VBATT + 50 mV. |
| VOUT (Pin 2) | Switched Output | Delivers up to 100 mA from VCC or VBATT; connects to RAM VDD for seamless backup power. |
| VCC (Pin 3) | Main Supply Input | 5 V nominal input; powers internal circuitry and sources VOUT until switchover condition occurs. |
| GND (Pin 4) | Ground Reference | 0 V reference for all analog comparators, digital outputs, and internal bias networks. |
| BATT ON (Pin 5) | Battery Status Output | Active-high open-drain signal indicating VBATT is active on VOUT; drives PNP base for >100 mA loads. |
| LOW LINE (Pin 6) | Active-High Reset Indicator | Inverts RESET; goes high when VCC falls below 4.65 V-used for processors requiring active-high reset. |
| OSC IN (Pin 7) | Oscillator Control Input | Selects watchdog period (100 ms/1.6 s) when OSC SEL high; accepts external clock or capacitor for adjustable timing. |
| OSC SEL (Pin 8) | Oscillator Mode Select | High/floating = internal oscillator; low = external clock/capacitor mode; includes 5 μA internal pull-up. |
| PFI (Pin 9) | Power-Fail Input | Non-inverting comparator input; triggers PFO low when voltage <1.3 V-monitors auxiliary supplies or battery level. |
| PFO (Pin 10) | Power-Fail Output | Open-drain output asserting low on PFI <1.3 V; used to trigger system save routines before main supply collapse. |
| WDI (Pin 11) | Watchdog Input | Three-level input (0.8 V/3.5 V thresholds); reset on missing edge within timeout; disabled if floating or at midsupply. |
| CEOUT (Pin 12) | Gated Chip Enable Output | Replicates CEIN only when VCC ≥ 4.65 V; forced high during reset to block RAM writes during brownout. |
| CEIN (Pin 13) | Chip Enable Input | Directly connected to processor CE/CS line; gated by internal supervisor logic to enforce data integrity. |
| WDO (Pin 14) | Watchdog Output | Asserts low on watchdog timeout; resets on next WDI transition or LOW LINE assertion-enables fault logging. |
| RESET (Pin 15) | Active-Low Reset Output | Drives microprocessor reset pin; remains valid down to VCC = 1 V; includes 3 μA internal pull-up. |
| RESET (Pin 16) | Active-High Reset Output | Complement of Pin 15; provides active-high reset for processors lacking internal inverter. |
Key Features
| Feature | Design Value |
|---|---|
| Adjustable Reset & Watchdog Timing | Configurable via OSC SEL/OSC IN to support diverse firmware architectures without changing BOM. |
| 3 ns CE Gating Propagation | Prevents metastable writes to battery-backed RAM during sub-millisecond supply transients. |
| 0.4 μA Battery Backup Current | Extends lithium or supercapacitor backup life to years in standby-critical for unattended systems. |
| VCC Monitoring Down to 1 V | Ensures controlled shutdown even during deep brownouts where most supervisors lose functionality. |
| Integrated Power-Fail Warning (PFI/PFO) | Enables deterministic data save sequences before VCC collapse-no external comparator required. |
Applications
| Industrial PLC Controller | Automotive Infotainment Head Unit |
|---|---|
Use Scenario: Maintains RAM state during engine cranking-induced 5 V rail sag (down to 3.5 V for 100 ms). IC Role / Device Role / Timing Role: Supervisory IC providing brownout reset, battery switchover, and CE gating to preserve configuration data. Use Value: Prevents EEPROM corruption and enables instant resume after voltage recovery-no reinitialization delay. | Use Scenario: Powers backup RAM during ignition-off power-down sequence while preserving user settings and radio presets. IC Role / Device Role / Timing Role: Dual-role supervisor: manages VCC/VBATT switchover and generates timed reset for MCU safe shutdown. Use Value: Eliminates need for discrete PNP switch and external reset controller-reduces board area by 35%. |
| Medical Patient Monitor | Network Router with Persistent Configuration |
Use Scenario: Retains real-time vital sign buffers during brief AC mains interruption (<200 ms). IC Role / Device Role / Timing Role: Precision reset generator with 50 ms pulse and watchdog supervision of safety-critical firmware. Use Value: Meets IEC 60601-1 requirement for uninterrupted data logging during Class I power faults. | Use Scenario: Preserves routing tables and security keys during unexpected power loss in enterprise edge devices. IC Role / Device Role / Timing Role: Combines PFI-based early warning, PFO-triggered save interrupt, and CEOUT-driven write lock. Use Value: Guarantees zero packet loss and configuration rollback on restore-no manual reconfiguration needed. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX691ACPE+ | Fixed 50 ms reset, no CE gating, no adjustable watchdog; 8-pin PDIP/SOIC only. | Lacks RAM write protection and flexible timing-suitable only for basic reset-only designs. | Choose only if design requires legacy pinout compatibility and omits battery-backed memory protection. |
| TPS3823MPW | Single 3.3 V reset threshold (3.08 V), no battery switchover, no WDO or CEOUT outputs. | Designed for low-voltage microcontrollers-not compatible with 5 V systems or backup RAM requirements. | Select only for new 3.3 V embedded designs without battery backup or watchdog needs. |
Compared with MAX691ACPE+ and TPS3823MPW, the ADM8691AN uniquely integrates battery switchover, CE gating, and dual-mode watchdog in a single 16-pin TSSOP-enabling compact, fail-safe 5 V microprocessor systems without supplemental ICs.
Availability
ADM8691AN is available at Aetrix Electronics and suitable for industrial PLC controllers, automotive infotainment head units, medical patient monitors, and network routers requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ADM8691AN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.
The ADM8691AN belongs to Analog Devices' microprocessor supervisory product line, engineered specifically for robust power monitoring, battery-backed memory protection, and deterministic reset sequencing in mission-critical 5 V embedded systems.
FAQ
What is the minimum VCC voltage at which ADM8691AN guarantees RESET assertion?
The ADM8691AN guarantees RESET assertion down to VCC = 1 V. This ensures the microprocessor remains held in reset during deep brownout conditions where other supervisors lose functionality. The RESET output remains valid and actively driven even at this ultra-low supply voltage, enabling reliable system shutdown sequencing in harsh electrical environments.
How does the ADM8691AN handle battery switchover hysteresis, and why is it critical?
The ADM8691AN uses 20 mV hysteresis in its battery switchover circuit: switchover occurs at VCC − VBATT = 70 mV on rising VCC and 50 mV on falling VCC. This prevents rapid toggling when VCC decays slowly near VBATT voltage-ensuring stable VOUT delivery to RAM during marginal power conditions and avoiding data corruption from supply chatter.
Can the ADM8691AN's watchdog timer be disabled, and how?
Yes, the ADM8691AN watchdog timer can be disabled by leaving the WDI pin floating or driving it to midsupply (~2.5 V). In either state, the internal watchdog circuit halts timing, and WDO remains high. This allows safe deactivation during debug or bootloader phases without hardware modification-verified in Analog Devices Rev. C datasheet Section "Watchdog Timer RESET".
What is the purpose of the CEIN and CEOUT pins on the ADM8691AN, and how do they protect memory?
The CEIN and CEOUT pins implement hardware-enforced write protection: CEOUT replicates CEIN only when VCC ≥ 4.65 V; below threshold, CEOUT is forced high to disable chip enable. This blocks writes to battery-backed RAM during brownout-preventing partial writes and data corruption. The 3 ns propagation delay ensures protection engages before supply collapse affects memory timing margins.
Does the ADM8691AN support both active-high and active-low reset outputs, and how are they used?
Yes, the ADM8691AN provides both RESET (Pin 15, active-low) and RESET (Pin 16, active-high) outputs. The active-low RESET drives standard microprocessor reset inputs, while the complementary active-high RESET serves processors requiring non-inverted reset signals-eliminating need for external inverters and reducing BOM count and layout complexity in mixed-architecture designs.
ADM8691AN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Push-Pull, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- 35ms Minimum
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
ADM8691AN FAQ
1.How can I place an order for ADM8691AN through Aetrix?
Please submit a Request for Quotation (RFQ) for ADM8691AN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADM8691AN reliable?
The price and inventory of ADM8691AN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADM8691AN is usually 5 days.
3.What payment methods are accepted for ADM8691AN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADM8691AN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADM8691AN?
ADM8691AN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADM8691AN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADM8691AN?
For technical support, including ADM8691AN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADM8691AN requirements.
6.How does Aetrix verify that ADM8691AN is sourced from the original manufacturer or authorized distributors?
All ADM8691AN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADM8691AN meets industry standards.
7.What is the process for return or replacement of ADM8691AN?
All ADM8691AN units undergo pre-shipment inspection (PSI). If there is an issue with ADM8691AN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADM8691AN part is unused and in its original packaging.
Return procedure for ADM8691AN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADM8691AN Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

