Analog Devices Inc. ADM8697ARW

Overview

ADM8697ARW from Analog Devices is a microprocessor supervisory circuit with integrated chip enable (CE) gating, low-line voltage monitoring, watchdog timer, and power-fail detection. It features 50 ms reset timeout, 1.6 s/100 ms selectable watchdog periods, 1.3 V LLIN threshold, CE propagation delay of 2–7 ns, and operates from 3.0 V to 5.5 V VCC. It is used in embedded controllers and automotive systems requiring reliable RAM write protection during brownout.

For engineers reviewing the ADM8697ARW datasheet, ADM8697ARW pinout, ADM8697ARW application, or ADM8697ARW equivalent, key selection criteria include CEIN/CEOUT timing integrity under low-VCC conditions, battery-backed RAM write-protection behavior during LLIN transitions, watchdog timeout configurability via OSC SEL/OSC IN, and compatibility with 3 V/5 V µP I/O logic levels.

Technical Context

The ADM8697ARW implements dual-mode oscillator control: internal 10.24 kHz oscillator (OSC SEL high/floating) or external clock/capacitor (OSC SEL low), enabling precise reset pulse width and watchdog timeout tuning. Its CE gating path uses fast CMOS logic with 2 ns propagation delay at 5 V, and forces CEOUT high when LLIN falls below 1.3 V-ensuring write protection independent of CEIN state.

It integrates a precision 1.3 V bandgap reference shared across LLIN, PFI, and internal comparators, with ±15 mV threshold matching and 12 mV hysteresis on LLIN for noise immunity. In battery backup mode (VCC < VBATT − 0.2 V), CEIN and CEOUT are internally disconnected and CEOUT defaults high at VOUT potential, preserving RAM data integrity without external intervention.

Key Specifications

Pinout & Package

ADM8697ARW is supplied in a 16-pin SOIC (R-16) package with 1.27 mm pitch, JEDEC MS-012AC compliant, thermal impedance θ_JA = 110°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX697CPE+ and TPS3823DBVR, ADM8697ARW uniquely combines sub-2 ns CE gating, dual-voltage-range operation (3–5.5 V), and brownout-triggered write blocking-making it the only option for safety-critical, battery-backed memory systems requiring guaranteed data integrity during supply transients.

Availability

ADM8697ARW is available at Aetrix Electronics and suitable for industrial controllers, automotive infotainment units, medical diagnostic equipment, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADM8697ARW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The ADM8697ARW belongs to Analog Devices' microprocessor supervisory IC product line, designed specifically for fail-safe power monitoring and memory write protection in mission-critical embedded systems operating across –40°C to +85°C.

FAQ

What is the minimum VCC voltage at which ADM8697ARW guarantees RESET assertion?

ADM8697ARW guarantees RESET assertion down to VCC = 1 V. At this level, RESET output voltage remains ≤20 mV with 10 µA sink current, ensuring reliable microprocessor hold-down even during deep brownout. This specification is validated across the full industrial temperature range (–40°C to +85°C) and is critical for systems requiring fail-safe shutdown before complete power collapse. The ADM8697ARW achieves this using a dedicated low-VCC charge pump and rail-to-rail comparator design not found in standard reset ICs.

How does ADM8697ARW handle CEIN during battery backup mode?

During battery backup mode (VCC < VBATT − 0.2 V), ADM8697ARW internally disconnects CEIN from its pull-up and sensing circuitry-eliminating input leakage and preventing unintended CEOUT transitions. CEOUT is forced high at VOUT potential, ensuring continuous write protection for backup RAM regardless of CEIN state. This behavior is documented in Table II of the ADM8697 datasheet and verified in typical application circuits Figure 18a/b. The ADM8697ARW maintains this state until VCC rises above the switchover threshold.

Can ADM8697ARW's watchdog timer be disabled in-system without hardware modification?

Yes-ADM8697ARW's watchdog timer can be disabled in-system by driving WDI to midsupply (≈VCC/2) or leaving it floating. In either case, the internal watchdog circuit detects absence of valid logic transitions and disables timeout enforcement, causing WDO to remain high and RESET to ignore WDI activity. This method is explicitly supported in the datasheet's "Watchdog Timer RESET" section and requires no external components. However, for safety-critical applications, permanent disablement is discouraged; the ADM8697ARW provides programmable timeout extension (e.g., 100 s via external capacitor) as a safer alternative.

What is the function of the TEST pin on ADM8697ARW, and how should it be connected?

The TEST pin (Pin 1) on ADM8697ARW is a factory test node used exclusively during wafer sort and final test; it has no user-accessible function in normal operation. Per the datasheet Pin Function Description, TEST must be connected to GND in all application circuits to ensure proper internal biasing and avoid undefined behavior. Leaving it floating may cause increased supply current or erratic reset timing. This requirement applies universally to all ADM8697ARW units and is independent of package variant (SOIC/RU-16).

Does ADM8697ARW support both 3 V and 5 V microprocessor I/O logic levels on CEIN and CEOUT?

Yes-ADM8697ARW supports both 3 V and 5 V µP I/O logic levels. CEIN thresholds are specified as VIL = 0.8 V (both 3 V and 5 V operation) and VIH = 3.0 V (5 V) or 1.2 V (3 V), ensuring compatibility with TTL and CMOS families. CEOUT drives to VCC − 0.5 V (min) with 800 µA source current, meeting VOH requirements for 3 V and 5 V receivers. Propagation delay is characterized at both VCC = 3 V (4 ns) and VCC = 5 V (2 ns), confirming full interoperability. This dual-voltage capability is intrinsic to the ADM8697ARW's design and requires no external level-shifting.