Analog Devices Inc. ADP1763ACPZ0.95-R7

Overview

ADP1763ACPZ0.95-R7 from Analog Devices is a 3 A, low-noise, low-dropout linear regulator optimized for ultra-sensitive analog and RF power domains. It operates from 1.10 V to 1.98 V input, delivers fixed 0.95 V output with ±1.5% accuracy over line/load/temperature, achieves 95 mV typical dropout at 3 A, and generates only 2 µV_rms (100 Hz–100 kHz) noise - enabling direct powering of PLLs, ADCs, and VCOs in automotive radar modules.

For engineers reviewing the ADP1763ACPZ0.95-R7 datasheet, ADP1763ACPZ0.95-R7 pinout, ADP1763ACPZ0.95-R7 application, or ADP1763ACPZ0.95-R7 equivalent, key selection criteria include ultralow noise spectral density (4 nV/√Hz @ 10 kHz), precision enable thresholds (625 mV typ.), power-good accuracy (±5% trip hysteresis), and AEC-Q100 qualification for automotive thermal cycling and reliability validation.

Technical Context

The ADP1763ACPZ0.95-R7 implements a proprietary LDO architecture with internal reference, error amplifier, and pass device forming a negative feedback loop. Its 0.5 V internal reference and 3.0 gain factor enable precise adjustable output scaling via external resistor on VADJ, while the 10 µA soft-start current source charges an external capacitor to control ramp-up time.

It integrates precision enable with 45 mV hysteresis to prevent oscillation during noisy transitions, open-drain power-good with 95% rising/92.5% falling thresholds, and dual protection: 4 A typical current limit and thermal shutdown at 150°C with 15°C hysteresis - all operating within −40°C to +125°C junction range.

Key Specifications

Pinout & Package

ADP1763ACPZ0.95-R7 uses a 16-lead, 3 mm × 3 mm LFCSP package with exposed thermal pad (EP) connected to GND. The package supports high-power dissipation in compact automotive and industrial PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with TPS7A8300RGRT and NCP1117ST095T3G, ADP1763ACPZ0.95-R7 uniquely balances sub-1 V operation, automotive qualification, and ultralow noise in a 3 mm × 3 mm footprint - making it the sole option for next-generation ADAS and medical sensor power domains demanding simultaneous low-VIN, low-noise, and high-reliability operation.

Availability

ADP1763ACPZ0.95-R7 is available at Aetrix Electronics and suitable for automotive radar modules, high-speed data acquisition systems, FPGA-based edge AI accelerators, and industrial PLC real-time clock subsystems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADP1763ACPZ0.95-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.

The ADP1763ACPZ0.95-R7 belongs to Analog Devices' low-noise LDO family engineered specifically for noise-critical power domains in automotive radar, medical imaging, and high-fidelity data conversion - where PSRR, dropout, and spectral noise define system-level performance.

FAQ

What is the minimum input voltage required for stable operation of the ADP1763ACPZ0.95-R7?

The ADP1763ACPZ0.95-R7 requires a minimum input voltage of 1.10 V across its full operating temperature range (−40°C to +125°C). At 0.95 V output, this yields only 150 mV headroom - sufficient due to its 95 mV typical dropout voltage at 3 A. Operation below 1.10 V triggers undervoltage lockout, disabling output until VIN rises above 1.06 V.

Does the ADP1763ACPZ0.95-R7 support remote sense functionality, and how is it implemented?

Yes, the ADP1763ACPZ0.95-R7 supports remote output sensing via the SENSE pin (Pin 13). To implement, connect the SENSE trace directly to the load's power input point - minimizing IR drop between VOUT pins and the actual load. This configuration improves load regulation to ±0.12%/A and maintains 0.95 V accuracy under dynamic current steps up to 3 A.

How does the power-good (PG) pin of the ADP1763ACPZ0.95-R7 behave during startup and fault conditions?

The ADP1763ACPZ0.95-R7 PG pin is an open-drain output that transitions high only when VOUT reaches 95% of 0.95 V (0.9025 V) during startup and remains above 92.5% (0.87875 V) during normal operation. It drives low immediately upon thermal shutdown, current-limit activation, EN deactivation, or VOUT droop - providing deterministic sequencing feedback with 0.75 ms EN-to-PG delay.

Can the ADP1763ACPZ0.95-R7 be used in parallel configurations to increase output current beyond 3 A?

Yes, the ADP1763ACPZ0.95-R7 supports paralleling for up to 5 A total output. For stable current sharing, both devices must be configured for identical 0.95 V output, and identical ballast resistors (e.g., 5 mΩ) must be placed in series with each VOUT path. This configuration maintains ultralow noise and high PSRR while distributing thermal load across two packages.

What capacitor types and values are recommended for input and output filtering of the ADP1763ACPZ0.95-R7?

Analog Devices specifies 10 µF X5R or X7R ceramic capacitors (6.3 V or 10 V rating) for both input (VIN–GND) and output (VOUT–GND), with ESR ≤ 0.5 Ω. A 1 µF capacitor is required on REFCAP and VREG pins. Y5V/Z5U dielectrics are explicitly prohibited due to excessive capacitance loss under DC bias and temperature variation - which risks instability and degraded transient response.