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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Analog Devices Inc. ADP1763ACPZ1.25-R7

Name: ADP1763ACPZ1.25-R7
Brand: Analog Devices Inc.
SKU: ADP1763ACPZ1.25-R7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADP1763ACPZ1.25-R7

Manufacturer:: Analog Devices Inc.

Category:: Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Package:: 16-WFQFN Exposed Pad, CSP

Datasheet:: ADP1763ACPZ1.25-R7.pdf

Description:: IC REG LINEAR 1.25V 3A 16LFCSP

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Product details

Overview

ADP1763ACPZ1.25-R7 from Analog Devices is a 3 A, low-noise, low-dropout linear regulator optimized for ultra-sensitive analog and RF power domains. It operates from 1.10 V to 1.98 V input, delivers fixed 1.25 V output with ±1.5% accuracy over line/load/temperature, features 2 µV_rms (100 Hz–100 kHz) noise and 95 mV typical dropout at 3 A, and is used in FPGA core supplies and PLL voltage regulation where supply integrity is critical.

For engineers reviewing the ADP1763ACPZ1.25-R7 datasheet, ADP1763ACPZ1.25-R7 pinout, ADP1763ACPZ1.25-R7 application, or ADP1763ACPZ1.25-R7 equivalent, key selection criteria include ultralow noise spectral density (4 nV/√Hz @ 10 kHz), precision enable thresholds (625 mV typ.), power-good accuracy (±7.5% falling threshold), and AEC-Q100 qualification for automotive systems requiring stable low-VIN biasing.

Technical Context

The ADP1763ACPZ1.25-R7 implements a proprietary LDO architecture with internal reference, error amplifier, and pass device forming a negative feedback loop. Its 16-lead LFCSP package integrates four parallel VIN and four parallel VOUT pins to minimize IR drop and support 3 A continuous output with low thermal resistance (Ψ_JB = 29.31°C/W).

It features externally programmable soft start via SS pin (10 µA current source charging external capacitor), precision enable with 45 mV hysteresis, and open-drain power-good output with 95% rising/92.5% falling trip points relative to nominal V_OUT. The device uses no external bias supply and maintains regulation down to 1.10 V input.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Voltage	Fixed 1.25 V ±1.5% over line, load, and −40°C to +125°C - ensures stable core bias for noise-sensitive ICs without trimming.
Max Output Current	3 A continuous - supports high-current digital loads like FPGA I/O banks or DSP cores without derating at TJ ≤ 125°C.
Input Voltage Range	1.10 V to 1.98 V - enables direct regulation from advanced low-VDD rails (e.g., 1.2 V or 1.8 V system supplies) without auxiliary bias.
Output Noise	2 µV_rms (100 Hz–100 kHz); 4 nV/√Hz @ 10 kHz - preserves SNR in ADC/DAC signal chains and phase noise in VCOs.
Dropout Voltage	95 mV typical @ 3 A - allows operation with only 1.35 V input for 1.25 V output, maximizing efficiency in tight headroom applications.
PSRR	59 dB @ 10 kHz, 43 dB @ 100 kHz (3 A load) - suppresses switching noise from adjacent DC/DC converters feeding mixed-signal subsystems.
Enable Threshold	625 mV typical high-level; 580 mV typical low-level with 45 mV hysteresis - enables clean sequencing with standard logic-level control signals.
Power-Good Accuracy	±7.5% falling threshold, ±5% rising threshold - provides reliable system reset signaling during brownout or startup transitions.

Pinout & Package

ADP1763ACPZ1.25-R7 is housed in a 3 mm × 3 mm, 16-lead LFCSP package with exposed thermal pad (EP) connected to GND. The package supports high-current routing via four parallel VIN and four parallel VOUT pins, minimizing trace resistance and thermal impedance.

Pin/Terminal	Circuit Role	Design Meaning
1–4 VIN	Regulator input supply	All four pins must be connected to input rail; reduces current density and improves thermal performance at 3 A.
5 REFCAP	Reference filter capacitor node	Connects 1 µF capacitor to GND; stabilizes internal reference and prevents noise coupling into regulation loop.
6 VREG	Regulated amplifier supply	Bypass with ≥1 µF capacitor; isolates error amplifier supply from noisy input rail for improved PSRR.
7 GND	Ground reference	Common return for all circuitry; EP must be soldered to PCB ground plane for thermal and electrical integrity.
8 VADJ	Adjustable output setting pin	Left floating for fixed-output variants like ADP1763ACPZ1.25-R7; not used in this configuration.
9–12 VOUT	Regulated output	All four pins connect directly to load; lowers effective output impedance and improves transient response under step loads.
13 SENSE	Remote output sensing	Connects near load to compensate for PCB IR drop; enables accurate regulation at point-of-load.
14 SS	Soft start timing control	Accepts external capacitor (e.g., 10 nF) to set 0.6 ms startup time; limits inrush current and enables voltage sequencing.
15 PG	Open-drain power-good indicator	Requires external pull-up; asserts low if VOUT < 92.5% nominal, during shutdown, or thermal overload - enables system monitoring.
16 EN	Logic-enable input	Active-high with precision thresholds (580–625 mV); supports automatic startup when tied to VIN or microcontroller GPIO.

Key Features

Feature	Design Value
AEC-Q100 qualified	Rated for automotive applications (−40°C to +125°C junction), enabling use in infotainment, ADAS, and body control modules.
Ultralow noise architecture	2 µV_rms broadband noise and 4 nV/√Hz spectral density at 10 kHz - preserves signal fidelity in RF transceivers and high-resolution data converters.
Optimized for ceramic capacitors	Stable with only 10 µF X5R/X7R output capacitance - eliminates need for bulky tantalum or electrolytic caps, saving board space and cost.
Integrated protection	Current-limit (4 A typ.) and thermal shutdown (150°C trip, 135°C hysteresis) - prevents damage during short-circuit or overload events without external circuitry.
Power-good with sequencing support	PG output with 95% rising/92.5% falling thresholds and 0.75 ms delay - enables safe power-up/down sequencing in multi-rail systems.
Precision enable interface	EN pin with 45 mV hysteresis and sub-1 µA leakage - eliminates false triggering from noise and supports low-power MCU-controlled enable/disable.

Applications

RF Transceiver Power	FPGA Core Supply
Use Scenario: Providing clean bias to LTE/5G front-end transceivers operating at 1.25 V core voltage. IC Role / Device Role / Timing Role: Low-noise LDO delivering regulated 1.25 V to RF synthesizer and mixer blocks. Use Value: 2 µV_rms noise and 59 dB PSRR at 10 kHz prevent reciprocal mixing and maintain EVM < 2.5% in 64-QAM transmission.	Use Scenario: Supplying configurable logic fabric in Xilinx Artix-7 FPGAs requiring stable 1.25 V at up to 3 A peak current. IC Role / Device Role / Timing Role: Primary core regulator with fast load transient response (< 20 µs recovery) for dynamic logic switching. Use Value: Four parallel VOUT pins and 10 µF ceramic stability reduce output droop to < 25 mV during 2 A step load, preventing configuration errors.
Medical Imaging ADC Bias	Automotive Camera Module
Use Scenario: Powering 16-bit SAR ADCs in portable ultrasound systems where analog front-end SNR is critical. IC Role / Device Role / Timing Role: Ultra-low-noise analog supply decoupling switching noise from digital back-end. Use Value: 4 nV/√Hz noise spectral density at 10 kHz ensures > 92 dB SNR in 1 MSPS acquisition, meeting IEC 62304 Class C requirements.	Use Scenario: Regulating image sensor and ISP voltage in AEC-Q100-compliant rear-view camera modules. IC Role / Device Role / Timing Role: Automotive-grade LDO with PG output for ASIL-B functional safety monitoring. Use Value: Power-good assertion within 0.75 ms of valid output enables fail-safe camera initialization and diagnostic reporting per ISO 26262.

RF Transceiver Power

FPGA Core Supply

Use Scenario: Providing clean bias to LTE/5G front-end transceivers operating at 1.25 V core voltage.

IC Role / Device Role / Timing Role: Low-noise LDO delivering regulated 1.25 V to RF synthesizer and mixer blocks.

Use Value: 2 µV_rms noise and 59 dB PSRR at 10 kHz prevent reciprocal mixing and maintain EVM < 2.5% in 64-QAM transmission.

Use Scenario: Supplying configurable logic fabric in Xilinx Artix-7 FPGAs requiring stable 1.25 V at up to 3 A peak current.

IC Role / Device Role / Timing Role: Primary core regulator with fast load transient response (< 20 µs recovery) for dynamic logic switching.

Use Value: Four parallel VOUT pins and 10 µF ceramic stability reduce output droop to < 25 mV during 2 A step load, preventing configuration errors.

Medical Imaging ADC Bias

Automotive Camera Module

Use Scenario: Powering 16-bit SAR ADCs in portable ultrasound systems where analog front-end SNR is critical.

IC Role / Device Role / Timing Role: Ultra-low-noise analog supply decoupling switching noise from digital back-end.

Use Value: 4 nV/√Hz noise spectral density at 10 kHz ensures > 92 dB SNR in 1 MSPS acquisition, meeting IEC 62304 Class C requirements.

Use Scenario: Regulating image sensor and ISP voltage in AEC-Q100-compliant rear-view camera modules.

IC Role / Device Role / Timing Role: Automotive-grade LDO with PG output for ASIL-B functional safety monitoring.

Use Value: Power-good assertion within 0.75 ms of valid output enables fail-safe camera initialization and diagnostic reporting per ISO 26262.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS7A8300RGRT	2 A max output, 4 µV_rms noise, 1.1 V–3.3 V input, 0.8 V–3.3 V adjustable output - lower current, higher noise, wider input range.	Used in general-purpose low-noise apps where 3 A is not required; lacks AEC-Q100 rating.	Select when board space permits larger 5 mm × 5 mm QFN and automotive qualification is unnecessary.
NCP114AMX125TBG	300 mA max output, 25 µV_rms noise, 1.4 V–5.5 V input, fixed 1.25 V - insufficient current, higher noise, no PG or soft start.	Targeted at low-power microcontrollers or sensors; no protection or sequencing features.	Choose only for cost-sensitive, non-critical biasing where 3 A capability and automotive compliance are irrelevant.

Compared with TPS7A8300RGRT and NCP114AMX125TBG, ADP1763ACPZ1.25-R7 uniquely combines 3 A output, 2 µV_rms noise, AEC-Q100 qualification, and integrated PG/soft start in a 3 mm × 3 mm footprint - making it the sole option for space-constrained, high-reliability, high-current analog power domains.

Availability

ADP1763ACPZ1.25-R7 is available at Aetrix Electronics and suitable for FPGA core supplies, RF transceiver biasing, and automotive camera modules requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for ADP1763ACPZ1.25-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.

The ADP1763 series was designed specifically for ultra-low-noise, low-VIN power delivery in next-generation RF, medical imaging, and automotive electronics - addressing the demand for high-current, sub-2 µV_rms LDOs compatible with advanced process nodes.

FAQ

What is the maximum output current specification for ADP1763ACPZ1.25-R7?

The ADP1763ACPZ1.25-R7 delivers up to 3 A of continuous output current at junction temperatures ≤125°C. This rating is validated across the full operating temperature range (−40°C to +125°C) and supported by thermal design using the 3 mm × 3 mm LFCSP package's Ψ_JB = 29.31°C/W parameter. Derating applies above 125°C junction temperature per the datasheet's thermal characteristics table.

Does ADP1763ACPZ1.25-R7 require an external bias supply?

No, ADP1763ACPZ1.25-R7 operates from a single 1.10 V to 1.98 V input supply without any external bias requirement. Its internal architecture eliminates the need for a separate VBIAS rail, simplifying power tree design and reducing component count - a key advantage over legacy LDOs that mandate ≥2.5 V bias for operation.

How does the power-good (PG) function behave on ADP1763ACPZ1.25-R7?

The ADP1763ACPZ1.25-R7 PG pin is an open-drain output that asserts low when VOUT falls below 92.5% of nominal (1.25 V), during thermal shutdown, current-limit mode, or EN-driven shutdown. Its rising threshold is 95% of nominal, with a 0.75 ms delay from EN rising edge to PG assertion - enabling robust system-level power sequencing and fault detection in automotive and medical designs.

Can ADP1763ACPZ1.25-R7 be used with ceramic output capacitors smaller than 10 µF?

No - ADP1763ACPZ1.25-R7 requires a minimum 10 µF ceramic output capacitor (X5R or X7R dielectric) for guaranteed stability and transient performance. The datasheet specifies 7.0 µF as absolute minimum only after accounting for worst-case capacitance loss due to temperature, voltage bias, and tolerance; using <10 µF risks oscillation or excessive overshoot during load steps.

Is ADP1763ACPZ1.25-R7 qualified for automotive applications?

Yes, ADP1763ACPZ1.25-R7 is AEC-Q100 qualified for automotive applications (Grade 1: −40°C to +125°C). This qualification covers stress testing for temperature cycling, humidity, mechanical shock, and ESD - confirming suitability for use in infotainment systems, ADAS cameras, and body electronics where reliability under harsh environmental conditions is mandatory.

ADP1763ACPZ1.25-R7 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 16-WFQFN Exposed Pad, CSP

Packaging:: Tape & Reel (TR)

Product Status:: Active

Output Configuration:: Positive

Output Type:: Fixed

Number of Regulators:: 1

Voltage - Input (Max):: 1.98V

Voltage - Output (Min/Fixed):: 1.25V

Voltage - Output (Max):: -

Voltage Dropout (Max):: 0.145V @ 3A

Current - Output:: 3A

Current - Quiescent (Iq):: 8 mA

Current - Supply (Max):: 16 mA

PSRR:: 62dB ~ 33dB (10kHz ~ 1MHz)

Control Features:: Enable, Power Good, Soft Start

Protection Features:: Current Limit, Thermal Overload

Operating Temperature:: -40°C ~ 125°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-LFCSP (3x3)

ADP1763ACPZ1.25-R7 FAQ

1.How can I place an order for ADP1763ACPZ1.25-R7 through Aetrix?

Please submit a Request for Quotation (RFQ) for ADP1763ACPZ1.25-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADP1763ACPZ1.25-R7 reliable?

The price and inventory of ADP1763ACPZ1.25-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP1763ACPZ1.25-R7 is usually 5 days.

3.What payment methods are accepted for ADP1763ACPZ1.25-R7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP1763ACPZ1.25-R7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADP1763ACPZ1.25-R7?

ADP1763ACPZ1.25-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADP1763ACPZ1.25-R7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADP1763ACPZ1.25-R7?

For technical support, including ADP1763ACPZ1.25-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP1763ACPZ1.25-R7 requirements.

6.How does Aetrix verify that ADP1763ACPZ1.25-R7 is sourced from the original manufacturer or authorized distributors?

All ADP1763ACPZ1.25-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP1763ACPZ1.25-R7 meets industry standards.

7.What is the process for return or replacement of ADP1763ACPZ1.25-R7?

All ADP1763ACPZ1.25-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP1763ACPZ1.25-R7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADP1763ACPZ1.25-R7 part is unused and in its original packaging.

Return procedure for ADP1763ACPZ1.25-R7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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