Analog Devices Inc. ADP2114ACPZ-R2
- Part No.:
- ADP2114ACPZ-R2
- Manufacturer:
- Analog Devices Inc.
- Package:
- 32-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADP2114ACPZ-R2.pdf
- Description:
- IC REG BUCK ADJ SGL/DL 32LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP2114ACPZ-R2 from Analog Devices is a configurable dual-channel synchronous step-down DC-DC regulator supporting 2 A/2 A or 3 A/1 A dual-output modes, or 4 A single interleaved output. It operates from 2.75 V to 5.5 V input, delivers ±1.5% output voltage accuracy, and supports selectable switching frequencies up to 1.2 MHz - used in point-of-load regulation for telecom baseband processors and FPGA core supplies.
For engineers reviewing the ADP2114ACPZ-R2 datasheet, ADP2114ACPZ-R2 pinout, ADP2114ACPZ-R2 application, or ADP2114ACPZ-R2 equivalent, key selection criteria include dual-phase 180° phase shift for reduced input ripple, independent enable/PGOOD per channel, programmable soft start, and thermal/overcurrent protection with hiccup mode recovery.
Technical Context
The ADP2114ACPZ-R2 integrates two current-mode PWM controllers with dual-phase, 180° phase-shifted operation to minimize input capacitor RMS current. Its internal P-channel high-side and N-channel low-side MOSFETs feature RDS(ON) of 52 mΩ / 27 mΩ (at VIN = 5 V) per channel, enabling high efficiency up to 95% at full load.
It supports flexible configuration via SCFG (SYNC/CLKOUT direction), OPCFG (peak current limit and pulse-skip mode), and FREQ (300/600/1200 kHz or external sync 200 kHz–2 MHz). The error amplifiers provide 550 µA/V transconductance and ±1.5% reference accuracy over −40°C to +125°C junction temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.75 V to 5.5 V - supports single-supply operation from common intermediate rails (e.g., 3.3 V or 5 V system buses). |
| Output Configuration | Dual 2 A/2 A or 3 A/1 A, or single 4 A interleaved - enables flexible power partitioning for multi-rail SoC/FPGA designs. |
| Switching Frequency | Selectable 300/600/1200 kHz or externally synchronized 200 kHz–2 MHz - allows noise-sensitive systems to avoid critical frequency bands. |
| Output Voltage Accuracy | ±1.5% over −40°C to +125°C - ensures stable core voltage under thermal stress in industrial and automotive environments. |
| Phase Relationship | 180° inter-channel phase shift - reduces input ripple current by ~70%, permitting smaller bulk input capacitance. |
| Protection Features | Hiccup-mode overcurrent, thermal shutdown at 150°C, UVLO (2.75 V rising), and independent PGOOD - supports robust fault handling without external supervision circuitry. |
| Package | 32-lead 5 mm × 5 mm LFCSP with exposed thermal pad - provides low thermal resistance (θJA = 34°C/W) for high-power density layouts. |
Pinout & Package
ADP2114ACPZ-R2 uses a 32-lead, 5 mm × 5 mm LFCSP package with an exposed thermal pad connected to analog ground. Pin functions are validated per Analog Devices Rev. C datasheet Figure 3 and Table 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pin 1) | Analog/digital ground reference | Must connect to signal/analog ground plane before power ground - prevents noise coupling into control loop. |
| COMP1 / COMP2 (Pins 2, 7) | Error amplifier outputs | Connect RC compensation networks; tied together for multiphase operation to synchronize loop dynamics. |
| FREQ (Pin 3) | Oscillator frequency select | Resistor-to-GND sets nominal fSW: 8.2 kΩ → 600 kHz - enables precise EMI tuning without changing layout. |
| SYNC/CLKOUT (Pin 5) | Bidirectional sync interface | Configurable as input (external clock sync) or output (90°-shifted 2×fSW clock) - supports stackable multi-phase systems. |
| VIN1–VIN6 (Pins 25–27, 14–16) | High-side MOSFET power inputs | Three dedicated VIN pins per channel reduce trace inductance and improve current sharing across internal switches. |
| PGND1–PGND4 (Pins 22–20, 21) | Power ground returns | Four isolated PGND pins per channel minimize ground bounce and enhance thermal dissipation path integrity. |
| SW1–SW4 (Pins 24, 23, 18, 17) | Switch node outputs | SW1/SW2 (Ch1) and SW3/SW4 (Ch2) must be shorted per channel - defines LC filter connection points for each output. |
| EN1 / EN2 (Pins 28, 13) | Independent enable inputs | Logic-high active; allow staggered startup sequencing or dynamic channel disable for power gating. |
| PGOOD1 / PGOOD2 (Pins 29, 12) | Open-drain power-good indicators | Pull low when output deviates >±8% (UV) or >+16% (OV) - enables system-level power sequencing and fault reporting. |
Key Features
| Feature | Design Value |
|---|---|
| Optimized gate slew rate | Reduces high-frequency EMI emissions without external snubbers - critical for powering ADCs and RF transceivers. |
| Dual-phase 180° interleaving | Cuts input ripple current amplitude by ~70% vs. single-phase - lowers required input capacitance and board area. |
| Programmable soft start | Capacitor on SS1/SS2 sets ramp time (e.g., 10 nF = 1 ms) - prevents inrush current damage to upstream converters or connectors. |
| Configurable current limit | OPCFG resistor selects Ch1/Ch2 peak limits independently (e.g., 2.4–5.3 A) - enables asymmetric load handling for mixed-voltage rails. |
| Forced PWM or pulse-skip mode | OPCFG pin selects light-load operation mode - forced PWM maintains low-noise spectrum; pulse-skip maximizes light-load efficiency. |
Applications
| Baseband Processor Power | FPGA Core Supply |
|---|---|
Use Scenario: Dual-rail power delivery to LTE/5G baseband processors requiring 1.8 V I/O and 1.0 V core with tight transient response. IC Role / Device Role / Timing Role: Configured as 2 A/2 A dual-output regulator with 180° phase shift and 600 kHz fSW to meet dynamic current demands. Use Value: Achieves <±15 mV output deviation during 2 A step load (Figure 35), eliminating need for external transient response compensation. | Use Scenario: High-current core supply for Xilinx Artix-7 FPGA with 0.85–1.0 V rail and >3 A peak current. IC Role / Device Role / Timing Role: Operated in 4 A interleaved mode with 1.2 MHz fSW, leveraging dual-phase operation to reduce output ripple. Use Value: Delivers 92% efficiency at 3 A (Figure 7), minimizing thermal load in space-constrained PCBs. |
| Industrial PLC I/O Module | Medical Imaging Sensor Bias |
Use Scenario: Isolated 3.3 V and 5 V auxiliary rails for digital I/O and communication interfaces in DIN-rail mounted PLCs. IC Role / Device Role / Timing Role: Used in fixed 3.3 V/2 A and 5 V/2 A configuration with independent EN1/EN2 for controlled power-up sequencing. Use Value: ±1.5% output accuracy over −40°C to +125°C ensures reliable logic-level compatibility across operating temperature range. | Use Scenario: Low-noise bias supply for CMOS image sensor analog front-end requiring <10 mV p-p ripple at 1.2 V. IC Role / Device Role / Timing Role: Configured in forced PWM mode with optimized gate slew rate and 300 kHz fSW to suppress switching noise. Use Value: Measured EMI reduction enables direct placement near sensitive analog signal chains without shielding. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54227PWPR | Single-channel 2.5 A, 4.5–18 V input, no interleaving or dual-phase support | Lacks dual-output flexibility and 180° phase shift - suitable only for single-rail replacement | Select when only one regulated rail is needed and input voltage exceeds 5.5 V. |
| RTQ2132B-QT | Automotive-grade dual 3 A/3 A buck, AEC-Q100 qualified, 2.7–5.5 V input | Includes functional safety features (power-good monitoring, fault flag) not present in ADP2114ACPZ-R2 | Choose for automotive infotainment or ADAS where ASIL-B compliance is required. |
Compared with TPS54227PWPR and RTQ2132B-QT, the ADP2114ACPZ-R2 uniquely supports reconfigurable dual/single output topologies, 180° interleaving for ripple reduction, and bidirectional SYNC/CLKOUT - making it optimal for compact, multi-rail embedded systems where layout area and EMI are constrained.
Availability
ADP2114ACPZ-R2 is available at Aetrix Electronics and suitable for telecommunications infrastructure, industrial PLCs, and medical imaging equipment requiring stable component supply and long-term design-in support.
Supply support for ADP2114ACPZ-R2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.
The ADP2114ACPZ-R2 belongs to Analog Devices' Power Management product line, designed specifically for high-efficiency, low-noise point-of-load regulation in space-constrained, thermally demanding applications.
FAQ
What is the maximum supported switching frequency for ADP2114ACPZ-R2?
The ADP2114ACPZ-R2 supports a maximum internal switching frequency of 1.2 MHz when the FREQ pin is configured with a 27 kΩ resistor to GND. It can also be synchronized to an external clock up to 2 MHz in the 600 kHz configuration or 4 MHz in the 1.2 MHz configuration - verified in Table 1 and Figure 22 of the Rev. C datasheet.
Can ADP2114ACPZ-R2 operate with only one channel enabled?
Yes, ADP2114ACPZ-R2 supports independent channel control: EN1 and EN2 are separate logic inputs, allowing Channel 1 or Channel 2 to be disabled while the other remains active. When one channel is off, its quiescent current drops to ≤2.5 mA (IDDCh1 or IDDCh2), and the enabled channel maintains full regulation capability.
How is output voltage set on ADP2114ACPZ-R2?
ADP2114ACPZ-R2 supports both fixed and adjustable outputs. Fixed voltages (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V) are selected by connecting V1SET or V2SET to GND through specific resistor values (e.g., 4.7 kΩ for 1.2 V). Adjustable mode uses a resistor divider from VOUT to GND with FBx, referencing 0.6 V - detailed in Table 4 and Figure 1.
Does ADP2114ACPZ-R2 require external MOSFETs?
No, ADP2114ACPZ-R2 integrates all power switches: each channel contains a P-channel high-side MOSFET (RDS(ON) = 52 mΩ at 5 V) and an N-channel low-side MOSFET (RDS(ON) = 27 mΩ at 5 V). Only external inductors, input/output capacitors, and feedback resistors are required - confirmed in General Description and Figure 1.
What thermal protection features does ADP2114ACPZ-R2 include?
ADP2114ACPZ-R2 incorporates thermal shutdown at 150°C junction temperature with 25°C hysteresis, plus hiccup-mode overcurrent protection that cycles after eight consecutive current-limit events. These features are fully specified in Table 1 and Theory of Operation section - ensuring safe operation under overload or poor heatsinking conditions.
ADP2114ACPZ-R2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable (Programmable)
- Number of Outputs:
- 1 or 2
- Voltage - Input (Min):
- 2.75V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V)
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 4A, 2A
- Frequency - Switching:
- 300kHz, 600kHz, 1.2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LFCSP-WQ (5x5)
ADP2114ACPZ-R2 FAQ
1.How can I place an order for ADP2114ACPZ-R2 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2114ACPZ-R2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2114ACPZ-R2 reliable?
The price and inventory of ADP2114ACPZ-R2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2114ACPZ-R2 is usually 5 days.
3.What payment methods are accepted for ADP2114ACPZ-R2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2114ACPZ-R2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2114ACPZ-R2?
ADP2114ACPZ-R2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2114ACPZ-R2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2114ACPZ-R2?
For technical support, including ADP2114ACPZ-R2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2114ACPZ-R2 requirements.
6.How does Aetrix verify that ADP2114ACPZ-R2 is sourced from the original manufacturer or authorized distributors?
All ADP2114ACPZ-R2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2114ACPZ-R2 meets industry standards.
7.What is the process for return or replacement of ADP2114ACPZ-R2?
All ADP2114ACPZ-R2 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2114ACPZ-R2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2114ACPZ-R2 part is unused and in its original packaging.
Return procedure for ADP2114ACPZ-R2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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