Analog Devices Inc. ADP2116ACPZ-R7
- Part No.:
- ADP2116ACPZ-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 32-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADP2116ACPZ-R7.pdf
- Description:
- IC REG BUCK ADJ SGL/DL 32LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:1,729
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Product details
Overview
ADP2116ACPZ-R7 from Analog Devices is a configurable dual-channel synchronous step-down DC-DC regulator supporting 3 A/3 A or 3 A/2 A independent outputs, or 6 A combined interleaved output. It operates from 2.75 V to 5.5 V input, delivers ±1.5% reference accuracy, and supports selectable switching frequencies up to 2 MHz - ideal for point-of-load regulation in telecom and industrial power systems.
For engineers reviewing the ADP2116ACPZ-R7 datasheet, ADP2116ACPZ-R7 pinout, ADP2116ACPZ-R7 application, or ADP2116ACPZ-R7 equivalent, key selection criteria include dual-phase 180° phase shift for reduced input ripple, independent enable/power-good signals per channel, programmable soft start, and thermal/overcurrent protection with hiccup mode recovery.
Technical Context
The ADP2116ACPZ-R7 implements current-mode control with dual PWM channels operating in either independent or interleaved (180° phase-shifted) configurations. Its integrated P-channel high-side and N-channel low-side MOSFETs support peak current limits of 3.5–5.3 A per channel, configurable via OPCFG pin resistor selection.
It features a bidirectional SYNC/CLKOUT pin that functions as either external synchronization input (200 kHz–2 MHz) or internal 90° out-of-phase clock output, enabling stackable multiphase designs. The device uses an optimized gate slew rate to minimize EMI while maintaining fast transient response through error amplifier transconductance of 550 µA/V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.75 V to 5.5 V - supports single-supply operation from common intermediate bus rails (e.g., 3.3 V or 5 V). |
| Output Configurations | Configurable as dual 3 A/3 A, 3 A/2 A, or single 6 A interleaved - enables flexible board-level power architecture scaling. |
| Switching Frequency | 300 kHz / 600 kHz / 1.2 MHz fixed, or synchronized 200 kHz–2 MHz - allows noise-sensitive system timing alignment. |
| Reference Accuracy | ±1.5% over −40°C to +125°C - ensures stable output voltage across industrial temperature range without calibration. |
| Efficiency | Up to 95% at full load - reduces thermal load and improves power density in space-constrained applications. |
| Protection Features | Input UVLO, overcurrent hiccup mode (8-cycle threshold), thermal shutdown at 150°C - provides robust fault handling without external circuitry. |
| Package | 32-lead, 5 mm × 5 mm LFCSP with exposed thermal pad - enables high-power dissipation in compact footprint. |
Pinout & Package
ADP2116ACPZ-R7 is housed in a 32-lead, 5 mm × 5 mm LFCSP package with exposed thermal pad connected to signal/analog ground. Pin functions are validated per Analog Devices Rev. B datasheet Figure 3 and Table 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pin 1) | Analog/Digital Ground Reference | Must connect to signal/analog ground plane before power ground - critical for noise-sensitive feedback stability. |
| COMP1 / COMP2 (Pins 2, 7) | Error Amplifier Output | Connect RC compensation network to GND; tied together for multiphase operation to synchronize control loops. |
| FREQ (Pin 3) | Frequency Select Input | Resistor-to-GND sets switching frequency (300/600/1200 kHz); determines minimum on/off times and LC filter sizing. |
| SYNC/CLKOUT (Pin 5) | Bidirectional Clock Interface | Configured as sync input or 90° phase-shifted clock output via SCFG pin - enables multi-rail synchronization or stacked multiphase expansion. |
| VIN1–VIN6 (Pins 25–27, 14–16) | High-Side MOSFET Power Inputs | Three dedicated VIN pins per channel reduce IR drop and improve current sharing in high-current paths. |
| PGND1–PGND4 (Pins 22–20, 21) | Power Ground Returns | Separate PGND pins per switch leg minimize ground bounce and improve EMI performance in dual-phase layout. |
| SW1–SW4 (Pins 24, 23, 18, 17) | Switch Node Outputs | SW1/SW2 for Channel 1; SW3/SW4 for Channel 2 - tie pairs together before LC filter to reduce loop area and parasitic inductance. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-phase interleaving | 180° phase shift between channels cuts input ripple current by ~50%, reducing required input capacitance and EMI filtering. |
| Configurable current limit | Selectable 3.5–5.3 A or 2.4–4.0 A per channel via OPCFG resistor - matches load requirements without overdesigning MOSFET stress. |
| Pulse skip vs. forced PWM | Light-load efficiency optimization (pulse skip) or noise-critical fixed-frequency operation (forced PWM) - selectable per application need. |
| Independent enable & PGOOD | EN1/EN2 and PGOOD1/PGOOD2 allow sequenced startup and per-rail fault monitoring - essential for multi-voltage FPGA/ASIC supplies. |
| EMI-optimized gate drive | Controlled slew rate minimizes high-frequency harmonics - simplifies compliance with CISPR 22/32 Class B emissions limits. |
Applications
| Telecom Point-of-Load | Industrial FPGA Core Supply |
|---|---|
|
Use Scenario: Regulating 1.2 V core voltage for high-speed FPGAs in 5G baseband cards with tight transient response requirements. IC Role / Device Role / Timing Role: Dual-channel buck controller delivering 3 A/3 A with 180° interleaving to meet <100 ns load-step response and <±2% output deviation. Use Value: Reduced input capacitor count (vs. single-phase) lowers BOM cost and PCB area while maintaining low output ripple (<10 mVpp). |
Use Scenario: Powering dual-voltage domains (1.8 V I/O and 0.85 V core) on programmable logic controllers with extended temperature operation. IC Role / Device Role / Timing Role: Independent channel configuration with separate EN/PGOOD enables safe power sequencing and rail-specific fault isolation. Use Value: ±1.5% reference accuracy and −40°C to +125°C operation ensure stable voltage under industrial ambient extremes without derating. |
| Medical Imaging Sensor Bias | Automotive Infotainment SoC |
|
Use Scenario: Generating ultra-low-noise 2.5 V bias for analog front-end ADCs in portable ultrasound systems. IC Role / Device Role / Timing Role: Forced PWM mode at 1.2 MHz avoids audible noise and interference with sensitive analog signal chains. Use Value: Optimized gate slew rate and 95% peak efficiency minimize self-heating and thermal drift in sealed medical enclosures. |
Use Scenario: Supplying 3.3 V and 1.2 V rails for infotainment SoCs in automotive dashboards with cold-crank immunity. IC Role / Device Role / Timing Role: Input UVLO (2.75 V threshold) and hiccup-mode overcurrent protection sustain operation during 4.5 V battery dips. Use Value: Dual-channel integration eliminates discrete regulators, reducing component count and improving ASIL-B functional safety compliance margin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS543B20RQFT | Single 3 A/3 A dual-channel buck with integrated MOSFETs; 4.5–18 V input; no adjustable frequency or SYNC/CLKOUT pin. | Targets higher-input industrial systems; lacks phase-shifted interleaving and external sync capability. | Choose when input >5.5 V is required and EMI constraints are less stringent. |
| ISL95831IRZ | 3+3 A dual-phase controller with external MOSFETs; supports VR12.5/IMVP7 protocols; no integrated power stage. | Designed for CPU/GPU VR applications requiring dynamic VID programming and telemetry. | Choose for server/desktop VRMs needing digital interface and adaptive voltage positioning. |
Compared with TPS543B20RQFT and ISL95831IRZ, the ADP2116ACPZ-R7 uniquely combines integrated dual MOSFET stages, 2.75–5.5 V input, 180° interleaving, and bidirectional clock I/O - making it optimal for compact, low-noise, mid-range input POL designs where integration and flexibility outweigh protocol-specific features.
Availability
ADP2116ACPZ-R7 is available at Aetrix Electronics and suitable for telecom infrastructure, industrial PLCs, and medical imaging systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for ADP2116ACPZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.
The ADP2116ACPZ-R7 belongs to Analog Devices' Power Management portfolio, designed specifically for high-efficiency, low-noise, configurable point-of-load regulation in space- and thermally-constrained embedded systems.
FAQ
What input voltage range does the ADP2116ACPZ-R7 support?
The ADP2116ACPZ-R7 supports an input voltage range of 2.75 V to 5.5 V. This makes it compatible with standard intermediate bus voltages such as 3.3 V and 5 V, and ensures reliable operation across wide variations including cold-crank conditions in automotive auxiliary systems. The device includes undervoltage lockout (UVLO) with 2.75 V rising threshold and 2.47 V falling threshold to prevent erratic startup.
How is output voltage configured on the ADP2116ACPZ-R7?
The ADP2116ACPZ-R7 supports both fixed and adjustable output voltages per channel. Fixed outputs (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V) are selected by connecting V1SET or V2SET to GND via specific resistor values per Table 4 in the datasheet. Adjustable mode uses a resistor divider from VOUT to GND with FBx pins, enabling outputs down to 0.6 V with ±1.5% reference accuracy over temperature.
Does the ADP2116ACPZ-R7 support synchronization with external clocks?
Yes, the ADP2116ACPZ-R7 supports external synchronization via its bidirectional SYNC/CLKOUT pin. When SCFG is tied to GND, the pin accepts an external clock from 200 kHz to 2 MHz. The internal oscillator frequency must be set close to the external clock using the FREQ pin resistor to ensure stable locking. This feature enables noise reduction in systems with multiple switching regulators.
What thermal protection mechanisms does the ADP2116ACPZ-R7 include?
The ADP2116ACPZ-R7 incorporates thermal shutdown at 150°C junction temperature with 25°C hysteresis, ensuring automatic recovery after cooling. It also features hiccup-mode overcurrent protection triggered after eight consecutive current-limit cycles, limiting power dissipation during sustained overload. These protections operate independently per channel and require no external components.
Can the ADP2116ACPZ-R7 operate in forced PWM mode?
Yes, the ADP2116ACPZ-R7 can operate in forced PWM mode, which maintains constant switching frequency even at light loads. This mode is selected via the OPCFG pin configuration and is ideal for noise-sensitive applications such as RF or high-resolution ADC circuits where pulse-skipping artifacts could interfere with signal integrity. Efficiency remains competitive down to ~10% load in this mode.
ADP2116ACPZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable (Programmable)
- Number of Outputs:
- 1 or 2
- Voltage - Input (Min):
- 2.75V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V)
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 6A, 3A/3A, 3A/2A
- Frequency - Switching:
- 300kHz, 600kHz, 1.2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LFCSP-WQ (5x5)
ADP2116ACPZ-R7 FAQ
1.How can I place an order for ADP2116ACPZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2116ACPZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2116ACPZ-R7 reliable?
The price and inventory of ADP2116ACPZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2116ACPZ-R7 is usually 5 days.
3.What payment methods are accepted for ADP2116ACPZ-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2116ACPZ-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2116ACPZ-R7?
ADP2116ACPZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2116ACPZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2116ACPZ-R7?
For technical support, including ADP2116ACPZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2116ACPZ-R7 requirements.
6.How does Aetrix verify that ADP2116ACPZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADP2116ACPZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2116ACPZ-R7 meets industry standards.
7.What is the process for return or replacement of ADP2116ACPZ-R7?
All ADP2116ACPZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2116ACPZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2116ACPZ-R7 part is unused and in its original packaging.
Return procedure for ADP2116ACPZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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