Analog Devices Inc. ADP2118ACPZ-1.0-R7
- Part No.:
- ADP2118ACPZ-1.0-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-WQFN Exposed Pad, CSP
- Datasheet:
-
ADP2118ACPZ-1.0-R7.pdf
- Description:
- IC REG BUCK 1V 3A 16LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP2118ACPZ-1.0-R7 from Analog Devices is a 3 A, synchronous step-down DC-DC regulator in a 4 mm × 4 mm LFCSP package, operating at fixed 1.2 MHz or 600 kHz switching frequency with ±1.5% output voltage accuracy. It delivers 1.0 V output from 2.3 V–5.5 V input, integrates 75 mΩ high-side and 40 mΩ low-side MOSFETs, and supports PFM mode for light-load efficiency-used in FPGA core voltage regulation requiring tight tracking and fast transient response.
For engineers reviewing the ADP2118ACPZ-1.0-R7 datasheet, ADP2118ACPZ-1.0-R7 pinout, ADP2118ACPZ-1.0-R7 application, or ADP2118ACPZ-1.0-R7 equivalent, key selection criteria include its 1.0 V preset output, integrated soft start (2048 clock cycles), power-good output with 110% rising threshold, and TRK pin-enabled voltage tracking for multi-rail sequencing in embedded processors.
Technical Context
The ADP2118ACPZ-1.0-R7 employs a current-mode, constant-frequency PWM architecture with slope compensation to ensure stability up to 100% duty cycle. Its transconductance error amplifier compares FB voltage against a 0.6 V internal reference and supports three inputs: reference, soft-start ramp, and TRK voltage-enabling precise output tracking of master supplies.
It features dual-mode operation: FPWM for full-load regulation with fixed 1.2 MHz switching (FREQ = VIN), and PFM for sub-100 mA loads to reduce quiescent current to 680 µA. Synchronization via SYNC/MODE pin supports phase-aligned or 180° out-of-phase operation across multiple regulators in dense PCB layouts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 3 A continuous-supports high-current FPGA core rails without external heatsinking. |
| Output Voltage | Fixed 1.0 V-eliminates external feedback resistors; optimized for low-voltage logic cores. |
| Input Range | 2.3 V to 5.5 V-compatible with single-cell Li-ion, USB 5 V, and intermediate bus architectures. |
| Switching Frequency | 1.2 MHz (FREQ = VIN)-enables compact 1 µH inductors and reduces output ripple in space-constrained designs. |
| Feedback Accuracy | ±1.5% over −40°C to +125°C-ensures reliable operation in industrial temperature environments. |
| Quiescent Current | 680 µA at no load (FPWM mode)-minimizes standby power in always-on subsystems. |
| Protection Features | UVLO (2.1 V fall), OVP (0.66 V FB threshold), OCP (5.2 A peak), thermal shutdown (140°C)-provides robust fault handling without external circuitry. |
Pinout & Package
ADP2118ACPZ-1.0-R7 is housed in a 16-lead, 4 mm × 4 mm LFCSP package with exposed thermal pad soldered to PGND plane for enhanced thermal dissipation (θJA = 38.3°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (SYNC/MODE) | Synchronization & mode control | Accepts external clock (600 kHz–1.4 MHz); logic level selects CCM-only (VIN) or PFM-enabled (GND) operation. |
| 2 (FREQ) | Frequency selection | Pull to GND for 600 kHz; pull to VIN for 1.2 MHz-determines inductor size and EMI profile. |
| 3 (TRK) | Voltage tracking input | Enables output to follow master supply (e.g., I/O rail) via resistor divider; critical for FPGA/ASIC sequencing. |
| 4 (FB) | Feedback sense | Internally tied to 1.0 V output; not user-configurable-simplifies layout and eliminates resistor tolerance errors. |
| 9–11 (SW) | Switch node | Drives external 1 µH power inductor; high di/dt path requiring short, low-inductance routing. |
| 12–13 (PVIN) | Power input | High-current input path for switch-side bypass capacitor; separate from bias rail (PIN 14) to reduce noise coupling. |
| 14 (VIN) | Bias input | Supplies internal circuitry; requires 10 Ω isolation resistor and local 0.1 µF decoupling to suppress supply noise. |
| 15 (EN) | Precision enable | 1.2 V typical turn-on threshold with 100 mV hysteresis; 1 MΩ internal pull-down prevents floating startup. |
| 16 (PGOOD) | Open-drain status flag | Asserts after FB reaches 110% of target (1.10 V) and holds for 16 clock cycles-validates stable 1.0 V rail before system boot. |
| 5, 6–8 (GND/PGND) | Analog & power ground | Separate AGND (PIN 5) and PGND (PINS 6–8) minimize noise coupling between control and power paths. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Power FETs | 75 mΩ P-channel high-side + 40 mΩ N-channel synchronous rectifier-enables >90% efficiency at 3 A, 1.0 V/3.3 V conversion. |
| Tracking Input (TRK) | Supports monotonic, ratio-matched startup with master rail (e.g., 1.0 V core tracking 3.3 V I/O)-prevents reverse current during power-up. |
| Start-Up into Precharged Output | Zero-reverse-current soft start prevents discharge of pre-biased output capacitors-essential for hot-swap and multi-rail systems. |
| Programmable Phase Shift | FREQ pin selects 0° or 180° synchronization phase-reduces input ripple in multi-phase configurations without external timing ICs. |
| Internal Compensation | Single-pole compensation network eliminates external Type II/III compensation components-reduces BOM count and layout sensitivity. |
Applications
| FPGA Core Voltage Regulation | Industrial PLC I/O Power |
|---|---|
|
Use Scenario: Supplying 1.0 V core rail for Xilinx Artix-7 or Intel Cyclone V FPGA under dynamic load (0–3 A). IC Role / Device Role / Timing Role: Primary point-of-load regulator delivering tightly regulated, low-noise 1.0 V with <10 µs transient recovery. Use Value: Integrated TRK pin enables synchronized ramp with 3.3 V I/O rail, preventing latch-up during configuration loading. |
Use Scenario: Generating isolated 1.0 V supply for analog front-end ADCs and DACs in programmable logic controllers. IC Role / Device Role / Timing Role: High-PSRR, low-ripple DC-DC stage filtering switching noise from upstream 5 V bus converters. Use Value: 1.2 MHz operation allows use of small 1 µH shielded inductors, reducing board area while maintaining >85% efficiency at 1.5 A. |
| Medical Imaging Sensor Bias | Automotive Infotainment SoC Core |
|
Use Scenario: Powering low-noise CMOS image sensor arrays requiring stable 1.0 V with <10 mV ripple in portable ultrasound devices. IC Role / Device Role / Timing Role: Final-stage regulator with PFM mode enabling <10 µA sleep current when sensor is idle. Use Value: ±1.5% output accuracy and −40°C to +125°C operation ensure consistent pixel response across clinical temperature ranges. |
Use Scenario: Delivering 1.0 V core voltage to NXP i.MX8M Mini SoC in automotive head units with strict EMC requirements. IC Role / Device Role / Timing Role: Synchronized 1.2 MHz buck converter aligned with system clock to shift noise away from AM/FM bands. Use Value: SYNC/MODE pin enables deterministic 180° phase offset between dual ADP2118s, halving input capacitor RMS current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62130ARGTR | 3 A, 3–17 V input, adjustable 0.9–6.05 V output; 2.25 MHz switching; no TRK pin or PFM mode. | Requires external feedback resistors; lacks voltage tracking-unsuitable for FPGA sequencing but better for wide-input industrial rails. | Choose TPS62130ARGTR when input exceeds 5.5 V or when higher switching frequency is needed to shrink magnetics. |
| RTQ2132BGQW | 3 A, 2.5–5.5 V input, fixed 1.0 V output; 1.5 MHz; includes spread-spectrum and enable-controlled soft-start. | No TRK pin; offers lower EMI via frequency dithering but no phase-shift sync capability. | Choose RTQ2132BGQW when EMI compliance (CISPR 25 Class 5) is critical and multi-regulator phase alignment is unnecessary. |
Compared with ADP2118ACPZ-1.0-R7, TPS62130ARGTR trades tracking and PFM flexibility for wider VIN range and higher frequency, while RTQ2132BGQW prioritizes EMI reduction over multi-rail coordination-making ADP2118ACPZ-1.0-R7 optimal for precision-tracking, thermally constrained FPGA/ASIC core supplies.
Availability
ADP2118ACPZ-1.0-R7 is available at Aetrix Electronics and suitable for FPGA core voltage regulation, industrial PLC I/O power, medical imaging sensor bias, and automotive infotainment SoC core applications requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for ADP2118ACPZ-1.0-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, and communications markets since 1965.
The ADP2118ACPZ-1.0-R7 belongs to Analog Devices' high-efficiency, low-voltage DC-DC regulator product line, designed specifically for powering advanced digital processors and ASICs where accuracy, tracking, and thermal performance are critical.
FAQ
What is the output voltage of the ADP2118ACPZ-1.0-R7?
The ADP2118ACPZ-1.0-R7 is a factory-trimmed, fixed-output regulator delivering 1.0 V ±1.5% over temperature and line. Unlike adjustable variants, it does not require external feedback resistors-its FB pin is internally connected to the 1.0 V output node, simplifying layout and improving accuracy by eliminating resistor tolerance and thermal drift effects.
Does the ADP2118ACPZ-1.0-R7 support voltage tracking, and how is it implemented?
Yes, the ADP2118ACPZ-1.0-R7 supports voltage tracking via its dedicated TRK pin. When a resistor divider from a master supply (e.g., 3.3 V I/O rail) is applied to TRK, the internal error amplifier regulates FB to match the scaled TRK voltage-enabling monotonic, ratio-controlled startup of the 1.0 V core rail relative to the master. If unused, TRK must be tied to VIN.
What protection features are integrated into the ADP2118ACPZ-1.0-R7?
The ADP2118ACPZ-1.0-R7 integrates undervoltage lockout (UVLO, 2.1 V fall), overvoltage protection (OVP, triggered at 0.66 V on FB), overcurrent protection (5.2 A peak limit), and thermal shutdown (140°C with 15°C hysteresis). All protections operate autonomously without external components, and fault recovery follows defined hiccup or restart sequences per the ADP2118ACPZ-1.0-R7 datasheet.
Can the ADP2118ACPZ-1.0-R7 operate with a precharged output capacitor?
Yes, the ADP2118ACPZ-1.0-R7 supports start-up into a precharged output. Its integrated soft-start circuit monitors the FB voltage and delays high-side switch activation until the soft-start ramp exceeds the precharged FB level-preventing reverse inductor current and uncontrolled discharge of the output capacitor, which is essential in hot-swap and multi-rail systems.
How does the ADP2118ACPZ-1.0-R7 handle light-load efficiency?
The ADP2118ACPZ-1.0-R7 improves light-load efficiency by automatically transitioning from FPWM to PFM mode when output current drops below the pulse-skipping threshold. In PFM mode, it reduces switching frequency and gate drive activity, lowering quiescent current to 680 µA-enabling >85% efficiency even at 10 mA load while maintaining regulation within ±1.5%.
ADP2118ACPZ-1.0-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.3V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1V
- Voltage - Output (Max):
- -
- Current - Output:
- 3A
- Frequency - Switching:
- 600kHz, 1.2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-LFCSP (4x4)
ADP2118ACPZ-1.0-R7 FAQ
1.How can I place an order for ADP2118ACPZ-1.0-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2118ACPZ-1.0-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2118ACPZ-1.0-R7 reliable?
The price and inventory of ADP2118ACPZ-1.0-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2118ACPZ-1.0-R7 is usually 5 days.
3.What payment methods are accepted for ADP2118ACPZ-1.0-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2118ACPZ-1.0-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2118ACPZ-1.0-R7?
ADP2118ACPZ-1.0-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2118ACPZ-1.0-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2118ACPZ-1.0-R7?
For technical support, including ADP2118ACPZ-1.0-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2118ACPZ-1.0-R7 requirements.
6.How does Aetrix verify that ADP2118ACPZ-1.0-R7 is sourced from the original manufacturer or authorized distributors?
All ADP2118ACPZ-1.0-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2118ACPZ-1.0-R7 meets industry standards.
7.What is the process for return or replacement of ADP2118ACPZ-1.0-R7?
All ADP2118ACPZ-1.0-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2118ACPZ-1.0-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2118ACPZ-1.0-R7 part is unused and in its original packaging.
Return procedure for ADP2118ACPZ-1.0-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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