Analog Devices Inc. ADP2118ACPZ-1.8-R7
- Part No.:
- ADP2118ACPZ-1.8-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-WQFN Exposed Pad, CSP
- Datasheet:
-
ADP2118ACPZ-1.8-R7.pdf
- Description:
- IC REG BUCK 1.8V 3A 16LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:1,604
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Product details
Overview
ADP2118ACPZ-1.8-R7 from Analog Devices is a 3 A, synchronous step-down DC-DC regulator in a 4 mm × 4 mm LFCSP package, operating at fixed 1.2 MHz or 600 kHz switching frequency with ±1.5% output voltage accuracy. It delivers 1.8 V output from 2.3–5.5 V input, integrates 75 mΩ high-side and 40 mΩ low-side MOSFETs, and supports PFM/PWM mode selection for high efficiency across load range - used in FPGA core voltage regulation requiring tight tracking and fast transient response.
For engineers reviewing the ADP2118ACPZ-1.8-R7 datasheet, ADP2118ACPZ-1.8-R7 pinout, ADP2118ACPZ-1.8-R7 application, or ADP2118ACPZ-1.8-R7 equivalent, key selection criteria include its 1.8 V preset output, integrated soft start, power-good signaling, voltage tracking capability, and thermal shutdown with 140°C trip point.
Technical Context
The ADP2118ACPZ-1.8-R7 employs a current-mode PWM control architecture with slope compensation to ensure stability up to 100% duty cycle. Its dual-mode operation (PWM for medium-to-full loads, PFM for light loads) enables >90% efficiency at 3 A and >85% at 10 mA under 5 V input.
It features precision enable with 1.2 V threshold and 100 mV hysteresis, a dedicated TRK pin for master-slave voltage tracking, and synchronized operation across 600 kHz–1.4 MHz with selectable 0° or 180° phase shift - all implemented without external compensation components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 3 A continuous - supports high-current FPGA I/O or processor core rails without external current boosting. |
| Output Voltage | Fixed 1.8 V - eliminates feedback resistor network, reduces BOM count and layout sensitivity. |
| Input Voltage Range | 2.3 V to 5.5 V - compatible with single-cell Li-ion, USB 5 V, and 3.3 V system rails. |
| Switching Frequency | 1.2 MHz (default) or 600 kHz - higher frequency enables smaller inductors (e.g., 1 µH); lower frequency improves light-load efficiency. |
| Efficiency | Up to 95% at 3 A (VIN = 5 V, VOUT = 1.8 V, FPWM) - minimizes thermal dissipation in space-constrained PCBs. |
| Protection Features | UVLO (2.1 V fall / 2.2 V rise), OVP (0.66 V FB threshold), OCP (5.2 A peak), thermal shutdown (140°C) - ensures robust operation in industrial environments. |
| Quiescent Current | 680 µA typical in switching no-load mode - extends battery life in always-on subsystems. |
Pinout & Package
ADP2118ACPZ-1.8-R7 is housed in a 16-lead, 4 mm × 4 mm LFCSP package with exposed thermal pad soldered to PGND plane. Pin 17 (EPAD) must be connected to a solid ground plane via thermal vias for optimal thermal performance (θJA = 38.3°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SYNC/MODE | Synchronization & mode control | Accepts external clock (600 kHz–1.4 MHz); logic-high enables CCM-only, logic-low enables PFM mode. |
| FREQ | Frequency selection | Logic-low selects 600 kHz; logic-high selects 1.2 MHz - sets base oscillator frequency before sync. |
| TRK | Voltage tracking input | Enables output to follow master rail (e.g., FPGA core voltage) via resistor divider; unused → tie to VIN. |
| FB | Feedback sense | Internally connected to 1.8 V reference; no external resistors required for this fixed-output variant. |
| SW (Pins 9–11) | Switch node | Drives external 1 µH inductor; three parallel pins reduce conduction loss and EMI. |
| PGND (Pins 6–8) | Power ground return | Low-impedance path for inductor current return; separate from analog GND to minimize noise coupling. |
| VIN / PVIN (Pins 12–14) | Bias & power input | VIN powers internal circuitry (via 10 Ω resistor); PVIN supplies high-current switch path - decoupling required on both. |
| EN | Precision enable | 1.2 V threshold with 100 mV hysteresis; internal 1 MΩ pull-down prevents floating startup. |
| PGOOD | Open-drain status flag | Asserts after soft start when FB reaches 105–115% of target; requires external pull-up <5.5 V. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Power Stage | 75 mΩ P-FET + 40 mΩ N-FET enables full 3 A output without external MOSFETs or gate drivers. |
| Tracking Function | TRK pin allows precise sequencing and voltage ramp matching with master supply - critical for multi-rail FPGAs/ASICs. |
| Start-Up into Precharged Output | Prevents reverse inductor current during hot-swap or partial-power-up scenarios - avoids output capacitor discharge. |
| Internal Compensation | No external compensation components needed - simplifies design, reduces footprint, and guarantees stability across operating conditions. |
| Soft Start | Fixed 2048-clock-cycle ramp (≈1.7 ms at 1.2 MHz) limits inrush current and controls output voltage slew rate. |
Applications
| Point-of-Load FPGA Core Supply | Industrial Sensor Node Power |
|---|---|
Use Scenario: Powers 1.8 V I/O banks of Xilinx Artix-7 or Intel Cyclone V FPGA during configuration and active operation. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering regulated 1.8 V with tracking to match core voltage ramp. Use Value: Integrated TRK and PGOOD enable safe power sequencing and fault reporting per Xilinx UG470 requirements. | Use Scenario: Supplies 1.8 V to ultra-low-power ARM Cortex-M4-based sensor fusion module with intermittent wake-up cycles. IC Role / Device Role / Timing Role: Main system regulator operating in PFM mode during sleep (10 µA IQ effective), switching to FPWM during data acquisition bursts. Use Value: 680 µA no-load quiescent current and automatic mode transition extend battery life beyond 5 years in coin-cell applications. |
| Medical Imaging Front-End | Automotive Infotainment SoC Rail |
Use Scenario: Provides clean, low-noise 1.8 V supply to high-speed ADC/DAC interface circuits in portable ultrasound systems. IC Role / Device Role / Timing Role: Secondary regulated rail derived from main 3.3 V domain; uses internal soft start and UVLO for controlled power-up sequence. Use Value: 38.3°C/W thermal resistance and thermal shutdown (140°C) ensure reliability under sealed enclosure conditions. | Use Scenario: Generates 1.8 V for DDR3L memory interface in automotive head-unit SoC (e.g., NXP i.MX8QuadMax) with ASIL-B functional safety constraints. IC Role / Device Role / Timing Role: Dedicated memory rail regulator with PGOOD monitoring and synchronization to system clock to reduce EMI coupling. Use Value: 1.2 MHz switching frequency allows use of small 1 µH shielded inductors meeting CISPR-25 Class 5 radiated emissions limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62172DSGR | 2 A max output, 3.0 V to 17 V input, 2.2 MHz fixed frequency, no TRK pin, 1% output accuracy | Lacks voltage tracking and 3 A capability; suited for lower-current, wider-input applications | Select when input exceeds 5.5 V or tracking is unnecessary; verify thermal margin at 2 A continuous load. |
| RT7295BGJ8F | 3 A output, 2.5 V to 5.5 V input, 1.5 MHz, no PFM mode, no TRK, requires external compensation | Higher minimum input voltage and no light-load efficiency optimization; lacks tracking and integrated soft start | Choose only if 1.5 MHz frequency is mandatory and board area allows external RC compensation network. |
Compared with TPS62172DSGR and RT7295BGJ8F, ADP2118ACPZ-1.8-R7 uniquely combines 3 A capability, 1.8 V fixed output, TRK-enabled sequencing, and seamless PFM/PWM transition - making it optimal for FPGA, SoC, and multi-rail embedded systems where precision tracking and wide-load-efficiency matter.
Availability
ADP2118ACPZ-1.8-R7 is available at Aetrix Electronics and suitable for FPGA power delivery, industrial sensor nodes, and medical imaging front-end designs requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for ADP2118ACPZ-1.8-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.
The ADP2118 product line delivers compact, high-efficiency synchronous buck regulators for point-of-load applications where space, thermal performance, and multi-rail sequencing are critical - especially in FPGA, DSP, and advanced SoC power systems.
FAQ
What is the output voltage tolerance of ADP2118ACPZ-1.8-R7 over temperature and line/load conditions?
ADP2118ACPZ-1.8-R7 maintains ±1.5% output voltage accuracy across −40°C to +125°C junction temperature, 2.3 V to 5.5 V input, and 0 A to 3 A load. This is verified by the FB regulation voltage specification (0.591 V to 0.609 V), which directly sets the 1.8 V output via internal resistor divider scaling - no external calibration required.
Can ADP2118ACPZ-1.8-R7 operate with a precharged output capacitor?
Yes, ADP2118ACPZ-1.8-R7 supports start-up into a precharged output. Its internal circuitry monitors the FB pin during soft start and prevents reverse inductor current until the soft-start voltage exceeds the precharged FB level - protecting the output capacitor and avoiding uncontrolled discharge.
Does ADP2118ACPZ-1.8-R7 require external compensation components?
No, ADP2118ACPZ-1.8-R7 features fully internal compensation. The error amplifier, slope compensation, and loop stability are factory-tuned for all operating conditions - eliminating the need for external capacitors or resistors in the compensation network and reducing design risk.
How does the TRK pin function in ADP2118ACPZ-1.8-R7, and what is its voltage range?
The TRK pin accepts 0–600 mV input and offsets the FB reference to enable output voltage tracking. When TRK = 0 mV, output follows internal 0.6 V reference (→ 1.8 V). For linear tracking, connect TRK to a resistor divider from a master rail - e.g., 1:2 divider from 3.3 V yields 1.65 V tracking point. ADP2118ACPZ-1.8-R7 regulates to the lowest of TRK, soft-start, or internal reference voltages.
What protection features are integrated into ADP2118ACPZ-1.8-R7?
ADP2118ACPZ-1.8-R7 integrates undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), thermal shutdown (140°C), and hiccup-mode short-circuit recovery. OVP triggers at 0.66 V on FB (≈115% of 1.8 V), OCP limits peak switch current to 5.2 A, and thermal hysteresis ensures restart only below 125°C.
ADP2118ACPZ-1.8-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.3V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V
- Voltage - Output (Max):
- -
- Current - Output:
- 3A
- Frequency - Switching:
- 600kHz, 1.2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-LFCSP (4x4)
ADP2118ACPZ-1.8-R7 FAQ
1.How can I place an order for ADP2118ACPZ-1.8-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2118ACPZ-1.8-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2118ACPZ-1.8-R7 reliable?
The price and inventory of ADP2118ACPZ-1.8-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2118ACPZ-1.8-R7 is usually 5 days.
3.What payment methods are accepted for ADP2118ACPZ-1.8-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2118ACPZ-1.8-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2118ACPZ-1.8-R7?
ADP2118ACPZ-1.8-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2118ACPZ-1.8-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2118ACPZ-1.8-R7?
For technical support, including ADP2118ACPZ-1.8-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2118ACPZ-1.8-R7 requirements.
6.How does Aetrix verify that ADP2118ACPZ-1.8-R7 is sourced from the original manufacturer or authorized distributors?
All ADP2118ACPZ-1.8-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2118ACPZ-1.8-R7 meets industry standards.
7.What is the process for return or replacement of ADP2118ACPZ-1.8-R7?
All ADP2118ACPZ-1.8-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2118ACPZ-1.8-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2118ACPZ-1.8-R7 part is unused and in its original packaging.
Return procedure for ADP2118ACPZ-1.8-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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