Analog Devices Inc. ADP2119ACPZ-1.2-R7
- Part No.:
- ADP2119ACPZ-1.2-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-VFDFN Exposed Pad, CSP
- Datasheet:
-
ADP2119ACPZ-1.2-R7.pdf
- Description:
- IC REG BUCK 1.2V 2A 10LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:840
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Product details
Overview
ADP2119ACPZ-1.2-R7 from Analog Devices is a synchronous step-down DC-to-DC regulator delivering up to 2 A continuous output current, fixed 1.2 V output voltage, 1.2 MHz switching frequency, ±1.5% output accuracy, and integrated high-side (145 mΩ) and low-side (70 mΩ) MOSFETs. It operates across 2.3 V–5.5 V input range and supports point-of-load power conversion in FPGA core supplies.
For engineers reviewing the ADP2119ACPZ-1.2-R7 datasheet, ADP2119ACPZ-1.2-R7 pinout, ADP2119ACPZ-1.2-R7 application, or ADP2119ACPZ-1.2-R7 equivalent, key selection criteria include fixed 1.2 V output, thermal performance in 3 mm × 3 mm LFCSP_WD package, PFM/PWM mode selection via SYNC/MODE pin, power-good flag, and voltage tracking capability for multi-rail sequencing.
Technical Context
The ADP2119ACPZ-1.2-R7 employs a current-mode, constant-frequency PWM control architecture with slope compensation to ensure stability at duty cycles >50%. Its integrated P-channel high-side and N-channel low-side MOSFETs enable high efficiency across load ranges, while internal compensation eliminates external loop components.
It supports selectable operation modes: fixed-frequency PWM (CCM) when SYNC/MODE = VIN, or pulse-frequency modulation (PFM) for light-load efficiency when SYNC/MODE = GND. The TRK pin enables precise voltage tracking of master rails, and the PGOOD open-drain output provides regulated power status with 110% rising threshold and 2.5% hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.2 V ±1.5% - ensures stable core supply for 1.2 V logic domains without external feedback resistors. |
| Max Output Current | 2 A continuous - supports high-current FPGA or ASIC core rails with minimal thermal derating in LFCSP_WD package. |
| Switching Frequency | 1.2 MHz (fixed), synchronizable 1–2 MHz - enables compact magnetics (e.g., 1.5 µH inductor) and reduces output capacitor size. |
| Input Voltage Range | 2.3 V to 5.5 V - compatible with single-cell Li-ion, 3.3 V, and 5 V intermediate bus architectures. |
| Quiescent Current | 680–900 µA (switching, no load) - minimizes standby power loss in always-on subsystems. |
| Protection Features | UVLO (2.3 V rising), OCP (3 A peak), OVP, thermal shutdown, and soft-start - ensures robust startup and fault recovery without external circuitry. |
| Efficiency @ 1.2 V/1 A | ~90% (VIN = 3.3 V, FPWM) - delivers high conversion efficiency at typical core rail operating points. |
Pinout & Package
ADP2119ACPZ-1.2-R7 uses a 10-lead, 3 mm × 3 mm LFCSP_WD package with exposed thermal pad soldered to PCB ground plane for optimal thermal dissipation (θJA = 40°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Bias voltage input | Supplies internal circuitry; requires 0.1 µF bypass capacitor and 10 Ω series resistor to PVIN for noise isolation. |
| PVIN | Main power input | Connects directly to input source (2.3–5.5 V); bypassed to PGND with bulk capacitor for high di/dt current handling. |
| SW | Switch node | Drives external inductor; connects high-side PMOS drain and low-side NMOS source - critical for EMI layout. |
| PGND | Power ground | High-current return path for MOSFETs; must be low-impedance copper plane tied to exposed pad. |
| GND | Analog ground | Reference for FB, EN, TRK, PGOOD; isolated from PGND except at single-point connection under exposed pad. |
| FB | Feedback sense | Internally connected to 1.2 V output; not used in fixed-version - shorted to VOUT internally per datasheet. |
| TRK | Tracking input | Enables output voltage to follow master rail (e.g., I/O supply); offset ≤±15 mV ensures tight tracking accuracy. |
| PGOOD | Power-good flag | Open-drain output asserting when FB ≥110% of target; requires external pull-up <5.5 V for system monitoring. |
| SYNC/MODE | Sync input / mode select | Configures CCM-only (SYNC = VIN) or auto PFM/PWM (SYNC = GND); accepts 1–2 MHz external clock for synchronization. |
| EN | Enable input | 1.2 V precision threshold with 100 mV hysteresis; internal 1 MΩ pull-down prevents floating enable. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Power Stages | 145 mΩ PMOS + 70 mΩ NMOS switches eliminate external MOSFETs and gate drivers, reducing BOM count and layout area. |
| Voltage Tracking | TRK pin supports accurate sequencing with master supplies (e.g., FPGA I/O vs. core), enabling safe power-up/down without external comparators. |
| Mode Flexibility | Hardware-selectable PFM (light-load efficiency) or forced PWM (low-noise, predictable EMI) via single SYNC/MODE pin connection. |
| Robust Protection Suite | Integrated UVLO, OVP, OCP, thermal shutdown, and soft-start prevent damage during faults, hot-plug, or precharged output conditions. |
| Internal Compensation | Eliminates external compensation network - simplifies design, improves production consistency, and reduces board space. |
Applications
| FPGA Core Supply | ASIC Processor Rail |
|---|---|
Use Scenario: Powering 1.2 V core logic of Xilinx Artix-7 or Intel Cyclone V FPGAs requiring tight voltage tolerance and fast transient response. IC Role / Device Role / Timing Role: Primary synchronous buck regulator providing regulated 1.2 V core voltage with PGOOD signaling for FPGA configuration lock. Use Value: Fixed 1.2 V output eliminates feedback resistor errors; 2 A rating supports dynamic current bursts; TRK pin enables coordinated ramp with 2.5 V I/O rail. | Use Scenario: Delivering stable 1.2 V supply to ARM Cortex-A9 or RISC-V SoC cores in industrial gateways with ambient temperatures up to +85°C. IC Role / Device Role / Timing Role: High-efficiency point-of-load converter with thermal shutdown and UVLO ensuring reliable operation under brownout or overheating. Use Value: 40°C/W θJA enables full 2 A output without heatsink; PFM mode extends battery life in always-on edge nodes; SYNC input allows EMI reduction via spread-spectrum clocking. |
| Communications Baseband | Medical Imaging Sensor Interface |
Use Scenario: Generating clean 1.2 V supply for LTE/5G baseband processors in small-form-factor remote radio units. IC Role / Device Role / Timing Role: Low-noise, high-PWM-frequency regulator minimizing interference with RF front-end; PGOOD enables processor reset coordination. Use Value: 1.2 MHz fixed frequency avoids sensitive IF bands; integrated soft start prevents inrush-induced voltage droop on shared 3.3 V bus. | Use Scenario: Powering low-noise analog front-end (AFE) and ADC reference circuits in portable ultrasound transducers. IC Role / Device Role / Timing Role: Precision-regulated 1.2 V rail with ±1.5% accuracy and low output ripple (<10 mV pk-pk) preserving signal integrity. Use Value: Internal compensation ensures stable loop response with ceramic output capacitors; TRK pin aligns AFE core voltage with digital controller rail for glitch-free sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62130ARGTR | 3 A output, 3–17 V input, 3.5 MHz switching, adjustable VOUT only | Requires external feedback resistors; higher input range suits 12 V intermediate bus; no TRK pin | Select when higher input voltage or output current is needed, and voltage tracking is unnecessary. |
| RT7297BZSP | 2 A output, 4.5–18 V input, 500 kHz–2.5 MHz programmable frequency, fixed 1.2 V option available | Wider input range but larger SO-8 package; no integrated soft start or PGOOD | Choose for cost-sensitive designs where thermal performance and power-good signaling are secondary. |
Compared with TPS62130ARGTR and RT7297BZSP, ADP2119ACPZ-1.2-R7 offers superior integration (no FB resistors, internal soft start, TRK, PGOOD), smaller footprint (3 mm × 3 mm vs. 3 mm × 3 mm QFN or SO-8), and optimized 1.2 V core regulation - making it ideal for space-constrained, multi-rail FPGA/ASIC systems requiring precise sequencing and reliability.
Availability
ADP2119ACPZ-1.2-R7 is available at Aetrix Electronics and suitable for FPGA core supplies, ASIC processor rails, communications baseband modules, medical imaging sensor interfaces, and industrial embedded controllers requiring stable component supply and long-term manufacturability.
Supply support for ADP2119ACPZ-1.2-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, communications, and healthcare markets.
The ADP2119ACPZ-1.2-R7 belongs to Analog Devices' ADP2119/ADP2120 family of compact, high-efficiency synchronous buck regulators designed specifically for low-voltage, high-current point-of-load applications in space-constrained portable and embedded systems.
FAQ
What is the output voltage tolerance of the ADP2119ACPZ-1.2-R7?
The ADP2119ACPZ-1.2-R7 has a guaranteed output voltage accuracy of ±1.5% over temperature (−40°C to +125°C), line, and load conditions. This specification is confirmed in the datasheet's "FB Regulation Voltage" table (VFB = 0.591 V to 0.609 V), corresponding to a fixed 1.2 V output derived from the internal 0.6 V reference and 2× resistor ratio - though no external resistors are required due to factory-trimmed configuration.
Does the ADP2119ACPZ-1.2-R7 require external compensation components?
No, the ADP2119ACPZ-1.2-R7 features fully internal compensation, eliminating the need for external RC networks. This is explicitly stated in both the General Description and Features sections of the datasheet and verified by the absence of compensation pins and the inclusion of "Internal compensation" as a key feature - simplifying design and improving production yield.
Can the ADP2119ACPZ-1.2-R7 operate with a precharged output capacitor?
Yes, the ADP2119ACPZ-1.2-R7 supports startup with a precharged output. Its integrated soft-start circuit monitors the FB pin voltage and holds both MOSFETs off until the soft-start ramp exceeds the precharged level, preventing reverse inductor current that could discharge the output capacitor - a behavior validated in Figure 25 of the datasheet.
What is the thermal resistance (θJA) of the ADP2119ACPZ-1.2-R7 package?
The ADP2119ACPZ-1.2-R7 in its 10-lead LFCSP_WD package has a specified junction-to-ambient thermal resistance (θJA) of 40°C/W under JEDEC 4-layer board conditions with the exposed pad soldered to PCB ground plane using thermal vias - enabling full 2 A output capability at +85°C ambient without additional heatsinking.
How does the TRK pin function in the ADP2119ACPZ-1.2-R7?
The TRK pin on the ADP2119ACPZ-1.2-R7 enables voltage tracking by feeding an external master voltage (via resistor divider) into the error amplifier's third positive input. The regulator then regulates FB to the lowest of three inputs: internal 0.6 V reference, soft-start ramp, or TRK voltage - allowing precise sequencing with I/O or auxiliary rails, as demonstrated in Figure 30 of the datasheet.
ADP2119ACPZ-1.2-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.3V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.2V
- Voltage - Output (Max):
- -
- Current - Output:
- 2A
- Frequency - Switching:
- 1.2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-LFCSP-WD (3x3)
ADP2119ACPZ-1.2-R7 FAQ
1.How can I place an order for ADP2119ACPZ-1.2-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2119ACPZ-1.2-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2119ACPZ-1.2-R7 reliable?
The price and inventory of ADP2119ACPZ-1.2-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2119ACPZ-1.2-R7 is usually 5 days.
3.What payment methods are accepted for ADP2119ACPZ-1.2-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2119ACPZ-1.2-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2119ACPZ-1.2-R7?
ADP2119ACPZ-1.2-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2119ACPZ-1.2-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2119ACPZ-1.2-R7?
For technical support, including ADP2119ACPZ-1.2-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2119ACPZ-1.2-R7 requirements.
6.How does Aetrix verify that ADP2119ACPZ-1.2-R7 is sourced from the original manufacturer or authorized distributors?
All ADP2119ACPZ-1.2-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2119ACPZ-1.2-R7 meets industry standards.
7.What is the process for return or replacement of ADP2119ACPZ-1.2-R7?
All ADP2119ACPZ-1.2-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2119ACPZ-1.2-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2119ACPZ-1.2-R7 part is unused and in its original packaging.
Return procedure for ADP2119ACPZ-1.2-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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