Analog Devices Inc. ADP2120ACPZ-1.8-R7
- Part No.:
- ADP2120ACPZ-1.8-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-VFDFN Exposed Pad, CSP
- Datasheet:
-
ADP2120ACPZ-1.8-R7.pdf
- Description:
- IC REG BUCK 1.8V 1.25A 10LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP2120ACPZ-1.8-R7 from Analog Devices is a fixed-output, 1.8 V, 1.25 A synchronous step-down DC-DC regulator in a 10-lead 3 mm × 3 mm LFCSP_WD package. It operates from 2.3 V to 5.5 V input, delivers ±1.5% output accuracy, features 1.2 MHz fixed switching frequency (synchronizable 1–2 MHz), and supports PWM/ PFM mode selection via SYNC/MODE pin for high efficiency across load range - used in FPGA core voltage regulation and portable power rails.
For engineers reviewing the ADP2120ACPZ-1.8-R7 datasheet, ADP2120ACPZ-1.8-R7 pinout, ADP2120ACPZ-1.8-R7 application, or ADP2120ACPZ-1.8-R7 equivalent, key selection criteria include its 1.25 A continuous output, integrated 145 mΩ/70 mΩ MOSFETs, precision enable threshold (1.2 V typ), power-good flag, and voltage tracking capability for multi-rail sequencing.
Technical Context
The ADP2120ACPZ-1.8-R7 employs a current-mode, constant-frequency PWM architecture with slope compensation to ensure stability up to 100% duty cycle. Its peak-current limit is 1.6–2.4 A (typ 2 A at 3.3 V), and it integrates soft start (1024 clock cycles, ~853 µs at 1.2 MHz) and precision feedback (0.6 V reference, ±1.5% accuracy).
It supports dynamic operation modes: FPWM for regulated light-load performance and PFM for ultra-low quiescent current (680–900 µA switching, <2 µA shutdown); voltage tracking enables coordinated startup with master supplies, and the TRK-to-FB offset is tightly controlled (±15 mV).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.8 V - eliminates external resistor divider, reduces BOM count and layout sensitivity. |
| Max Output Current | 1.25 A continuous - sufficient for low-power FPGA cores, microcontrollers, and DSP I/O rails. |
| Input Voltage Range | 2.3 V to 5.5 V - compatible with single-cell Li-ion, USB 5 V, and 3.3 V intermediate bus systems. |
| Switching Frequency | 1.2 MHz (fixed), synchronizable 1–2 MHz - enables compact LC filter design with ≤2.2 µH inductors. |
| Feedback Accuracy | ±1.5% over −40°C to +125°C - ensures stable core voltage under thermal stress in industrial environments. |
| Quiescent Current | 680–900 µA (switching, no load) - extends battery life in always-on portable subsystems. |
| Thermal Resistance | θJA = 40°C/W - requires exposed pad soldered to PCB ground plane for reliable 1.25 A operation at +85°C ambient. |
Pinout & Package
ADP2120ACPZ-1.8-R7 uses a 10-lead, 3 mm × 3 mm LFCSP_WD package with exposed thermal pad (EPAD) that must be soldered to PCB ground for thermal dissipation. Pin numbering follows top-view standard (pin 1 at top-left corner, counterclockwise).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pin 1) | Bias supply input | Provides gate drive bias; requires 0.1 µF bypass capacitor and 10 Ω series resistor to PVIN for noise isolation. |
| PVIN (Pin 2) | Main power input | High-current input node; connect directly to source with low-ESR input capacitor to PGND. |
| SW (Pin 3) | Switch node | Connects to inductor; carries high di/dt; requires tight layout and Kelvin connection to minimize ringing. |
| PGND (Pin 4) | Power ground return | High-current return path for MOSFETs; must tie directly to input/output capacitor ground planes. |
| GND (Pin 5) | Analog ground reference | Reference for FB, EN, TRK; separate from PGND to avoid noise coupling into feedback loop. |
| FB (Pin 6) | Feedback sense | Internally tied to 1.8 V output (fixed version); not user-connected - simplifies layout and eliminates divider error. |
| TRK (Pin 7) | Voltage tracking input | Enables output to follow master rail (e.g., FPGA VCCINT); connect to resistor divider or VIN if unused. |
| PGOOD (Pin 8) | Open-drain status flag | Asserts high when FB ≥ 105% of target; requires external pull-up (≤5.5 V) for system power sequencing. |
| SYNC/MODE (Pin 9) | Frequency sync / mode select | Drive with 1–2 MHz clock for synchronization; tie to VIN for FPWM-only, GND for PFM-enabled operation. |
| EN (Pin 10) | Enable control | 1.2 V typical threshold with 100 mV hysteresis; internal 1 MΩ pull-down prevents floating enable. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Power Stage | 145 mΩ high-side PMOS + 70 mΩ low-side NMOS - eliminates external MOSFETs and reduces conduction loss at 1.25 A. |
| Voltage Tracking | TRK pin accepts 0–600 mV input with ±15 mV offset - enables precise sequencing with master supplies (e.g., FPGA VCCIO tracking VCCINT). |
| Mode Flexibility | Pin-selectable FPWM/PFM via SYNC/MODE - maintains >85% efficiency from 1 mA to 1.25 A without external control logic. |
| Robust Protection Suite | UVLO (2.2 V rising), OCP (2 A typ), OVP, TSD (150°C), and soft-start - ensures safe startup and fault recovery in unattended systems. |
| Internal Compensation | Single-pole compensation network embedded - removes need for external compensation components, reducing design cycle time. |
Applications
| FPGA Core Power | Portable Medical Sensor |
|---|---|
Use Scenario: Powers Xilinx Spartan-7 or Intel MAX 10 FPGA core rail requiring tight voltage tolerance and clean startup sequencing. IC Role / Device Role / Timing Role: Primary 1.8 V core regulator with voltage tracking (TRK) and power-good (PGOOD) for coordinated rail bring-up. Use Value: Fixed 1.8 V output eliminates resistor mismatch errors; ±1.5% accuracy ensures FPGA timing margin compliance across temperature. | Use Scenario: Supplies low-noise 1.8 V rail to ADC front-end and microcontroller in handheld ECG monitor. IC Role / Device Role / Timing Role: High-efficiency point-of-load converter operating in PFM mode during standby, switching to FPWM during signal acquisition bursts. Use Value: 680 µA quiescent current extends battery life; 1.2 MHz switching allows small 1.5 µH inductor and 22 µF ceramic output cap. |
| Industrial PLC I/O Module | Automotive Infotainment MCU |
Use Scenario: Generates 1.8 V for ARM Cortex-M7-based controller in DIN-rail mounted PLC with wide ambient temperature range. IC Role / Device Role / Timing Role: Robust DC-DC regulator with thermal shutdown (150°C), UVLO, and 40°C/W θJA for convection-cooled enclosures. Use Value: Guaranteed operation from −40°C to +125°C junction; integrated soft start prevents inrush-induced brownouts on shared 3.3 V bus. | Use Scenario: Powers 1.8 V I/O domain of automotive-grade MCU in head unit, coexisting with CAN and audio subsystems. IC Role / Device Role / Timing Role: EMI-conscious buck converter synchronized to system clock (via SYNC/MODE) to avoid band interference. Use Value: 1–2 MHz synchronization range enables deterministic noise placement; LFCSP_WD package minimizes board area in space-constrained head unit PCB. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62172DSGR | 1.2 A max output, 2.5–5.5 V input, 2.25 MHz fixed frequency, no TRK pin, different pinout | Lacks voltage tracking and has lower current rating; suitable only where sequencing is handled externally | Select if higher switching frequency is prioritized over tracking and 1.25 A margin is acceptable |
| RT7295BGJ8F | 1.5 A max output, 2.5–5.5 V input, 1.5 MHz, integrated soft start, no PFM mode, different package (WDFN-10) | Higher current but no light-load PFM; lacks TRK and has no SYNC capability | Choose when FPWM-only operation suffices and 1.5 A headroom justifies trade-off in efficiency flexibility |
Compared with TPS62172DSGR and RT7295BGJ8F, ADP2120ACPZ-1.8-R7 uniquely combines 1.25 A capability, voltage tracking, PFM/FPWM mode selection, and 1.2 MHz synchronization - making it optimal for FPGA and multi-rail embedded systems requiring precise sequencing and wide-input, low-quiescent operation.
Availability
ADP2120ACPZ-1.8-R7 is available at Aetrix Electronics and suitable for FPGA core power, portable medical sensors, and industrial PLC I/O modules requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for ADP2120ACPZ-1.8-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The ADP2120ACPZ-1.8-R7 belongs to Analog Devices' ADP2119/ADP2120 family of compact, high-efficiency synchronous buck regulators designed specifically for low-voltage, medium-current point-of-load conversion in space- and power-constrained embedded systems.
FAQ
What is the maximum continuous output current of the ADP2120ACPZ-1.8-R7?
The ADP2120ACPZ-1.8-R7 delivers up to 1.25 A continuous output current under typical thermal conditions (θJA = 40°C/W, 25°C ambient, exposed pad soldered). This rating is validated across the full input range (2.3 V to 5.5 V) and output voltage (1.8 V), with derating required above +85°C ambient per thermal characteristics in the datasheet.
Does the ADP2120ACPZ-1.8-R7 require external feedback resistors?
No. The ADP2120ACPZ-1.8-R7 is a fixed-output variant with internal feedback set to 1.8 V; pin 6 (FB) is internally connected and must not be externally loaded. This eliminates resistor tolerance errors and simplifies layout versus adjustable versions like ADP2120ACPZ-R7.
How does the SYNC/MODE pin configure operation mode on the ADP2120ACPZ-1.8-R7?
When SYNC/MODE (pin 9) is tied to GND, the ADP2120ACPZ-1.8-R7 enables PFM mode for light-load efficiency; when tied to VIN, it forces FPWM-only operation. Applying an external 1–2 MHz clock synchronizes switching while enforcing CCM - all configurations retain full protection and tracking functionality.
Can the ADP2120ACPZ-1.8-R7 safely start up with a precharged output capacitor?
Yes. The ADP2120ACPZ-1.8-R7 includes reverse-current protection during startup: if the FB pin voltage exceeds the soft-start ramp at turn-on, both MOSFETs remain off until the ramp rises above FB, preventing output capacitor discharge through the inductor - critical for hot-swap and multi-rail systems.
What thermal design considerations apply to the ADP2120ACPZ-1.8-R7 package?
The ADP2120ACPZ-1.8-R7 uses a 10-lead LFCSP_WD package with an exposed thermal pad (EPAD) that must be soldered to a dedicated PCB ground plane using ≥4 thermal vias. Failure to do so degrades θJA from 40°C/W to >60°C/W, risking thermal shutdown at >0.8 A in still-air conditions.
ADP2120ACPZ-1.8-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.3V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V
- Voltage - Output (Max):
- -
- Current - Output:
- 1.25A
- Frequency - Switching:
- 1.2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-LFCSP-WD (3x3)
ADP2120ACPZ-1.8-R7 FAQ
1.How can I place an order for ADP2120ACPZ-1.8-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2120ACPZ-1.8-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2120ACPZ-1.8-R7 reliable?
The price and inventory of ADP2120ACPZ-1.8-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2120ACPZ-1.8-R7 is usually 5 days.
3.What payment methods are accepted for ADP2120ACPZ-1.8-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2120ACPZ-1.8-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2120ACPZ-1.8-R7?
ADP2120ACPZ-1.8-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2120ACPZ-1.8-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2120ACPZ-1.8-R7?
For technical support, including ADP2120ACPZ-1.8-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2120ACPZ-1.8-R7 requirements.
6.How does Aetrix verify that ADP2120ACPZ-1.8-R7 is sourced from the original manufacturer or authorized distributors?
All ADP2120ACPZ-1.8-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2120ACPZ-1.8-R7 meets industry standards.
7.What is the process for return or replacement of ADP2120ACPZ-1.8-R7?
All ADP2120ACPZ-1.8-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2120ACPZ-1.8-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2120ACPZ-1.8-R7 part is unused and in its original packaging.
Return procedure for ADP2120ACPZ-1.8-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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